Patents by Inventor Daniel Cutler
Daniel Cutler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9673109Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: GrantFiled: February 9, 2016Date of Patent: June 6, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Patent number: 9576887Abstract: In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.Type: GrantFiled: September 9, 2013Date of Patent: February 21, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Patent number: 9502395Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: GrantFiled: October 6, 2015Date of Patent: November 22, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Patent number: 9397212Abstract: In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.Type: GrantFiled: September 9, 2013Date of Patent: July 19, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Patent number: 9362221Abstract: According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.Type: GrantFiled: April 16, 2015Date of Patent: June 7, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Mark Pavier, Daniel Cutler, Scott Palmer, Clive O'Dell, Rupert Burbidge
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Publication number: 20160155674Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: ApplicationFiled: February 9, 2016Publication date: June 2, 2016Inventors: EUNG SAN CHO, ANDREW N. SAWLE, MARK PAVIER, DANIEL CUTLER
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Patent number: 9299690Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: GrantFiled: October 6, 2015Date of Patent: March 29, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Patent number: 9269655Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: GrantFiled: August 13, 2015Date of Patent: February 23, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Publication number: 20160035699Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: ApplicationFiled: October 6, 2015Publication date: February 4, 2016Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Publication number: 20160027767Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: ApplicationFiled: October 6, 2015Publication date: January 28, 2016Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Publication number: 20150348888Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Publication number: 20150348887Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Patent number: 9159703Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: GrantFiled: September 10, 2013Date of Patent: October 13, 2015Assignee: International Rectifier CorporationInventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Patent number: 9111921Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: GrantFiled: September 10, 2013Date of Patent: August 18, 2015Assignee: International Rectifier CorporationInventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Publication number: 20150221588Abstract: According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Inventors: Mark Pavier, Daniel Cutler, Scott Palmer, Clive O'Dell, Rupert Burbidge
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Patent number: 9012990Abstract: According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.Type: GrantFiled: September 4, 2013Date of Patent: April 21, 2015Assignee: International Rectifier CorporationInventors: Mark Pavier, Daniel Cutler, Scott Palmer, Clive O'Dell, Rupert Burbidge
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Publication number: 20140110776Abstract: In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.Type: ApplicationFiled: September 9, 2013Publication date: April 24, 2014Applicant: International Rectifier CorporationInventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Publication number: 20140110863Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.Type: ApplicationFiled: September 10, 2013Publication date: April 24, 2014Applicant: International Rectifier CorporationInventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Publication number: 20140110796Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.Type: ApplicationFiled: September 10, 2013Publication date: April 24, 2014Applicant: International Rectifier CorporationInventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
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Publication number: 20140110788Abstract: In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.Type: ApplicationFiled: September 9, 2013Publication date: April 24, 2014Applicant: International Rectifier CorporationInventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler