Patents by Inventor Daniel D. Claxton

Daniel D. Claxton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6847819
    Abstract: A wireless communication device, comprising one or more intra-device modules, an internet protocol (IP) router for providing inter-device connectivity between a host and the intra-device modules, and one or more transport mechanisms, for coupling the IP router to the host. One or more intra-device modules are accessed via a standard internetwork protocol as if the intra-device modules were local servers.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: January 25, 2005
    Assignee: Qualcomm Incorporated
    Inventors: Stephen A. Sprigg, Marc S. Phillips, Richard J. Kerr, Daniel D. Claxton
  • Patent number: 6178388
    Abstract: A method and apparatus for calibrating a resistive ladder switching matrix coupled to a keypad in a portable electronic device having a housing with a cover that may be positioned in an open state or a closed state. A first contact of a calibration element is coupled to a reference voltage and a second contact of the calibration element is coupled to ground by moving the cover from the open state to the closed state. When the first contact of the calibration element is coupled to the reference voltage and the second contact of the calibration element is coupled to ground, a calibration resistance across the calibration element is determined. The calibration resistance may correspond to an input impedance of the resistive ladder switching matrix when no buttons associated with the keypad are depressed. Signals from the resistive ladder switching network are calibrated when the cover is in the closed state in accordance with the calibration resistance.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: January 23, 2001
    Assignee: Qualcomm Incorporated
    Inventor: Daniel D. Claxton
  • Patent number: 5410671
    Abstract: A data compression/decompression processor (a single-chip VLSI data compression/decompression engine) for use in applications including but not limited to data storage and communications. The processor is highly versatile such that it can be used on a host bus or housed in host adapters, so that all devices such as magnetic disks, tape drives, optical drives and the like connected to it can have substantial expanded capacity and/or higher data transfer rate. The processor employs an advanced adaptive data compression algorithm with string-matching and link-list techniques so that it is completely adaptive, and a dictionary is constructed on the fly. No prior knowledge of the statistics of the characters in the data is needed. During decompression, the dictionary is reconstructed at the same time as the decoding occurs. The compression converges very quickly and the compression ratio approaches the theoretical limit. The processor is also insensitive to error propagation.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: April 25, 1995
    Assignee: Cyrix Corporation
    Inventors: Taher A. Elgamal, Daniel D. Claxton, Robert F. Honea