Abstract: In aspect an application may be configured to issue a request to store an object, with the request including an object reference. A delegate may be configured to receive the request to store the object, determine a hosted storage service, from among multiple hosted storage services, and a corresponding access protocol based on the object reference, and store the object in the hosted storage service using the corresponding protocol.

Abstract: In aspect an application may be configured to issue a request to store an object, with the request including an object reference. A delegate may be configured to receive the request to store the object, determine a hosted storage service, from among multiple hosted storage services, and a corresponding access protocol based on the object reference, and store the object in the hosted storage service using the corresponding protocol.

Abstract: The present invention provides the method and system that redistribute the nodes of a sorted tree to enable faster data insertion. Further, the tree typically contains a fixed number of levels, each comprising a fixed number of nodes. Each node in the tree is indexed and each leaf node may comprise a number of data segments. An increment is empirically calculated as space redistributed among non-empty leaf nodes. Furthermore, when a data segment is inserted and certain conditions are met, a data structure with a marked head and tail effectively “traverses” the tree from one end to the other searching for empty leaf nodes. In cases where the data structure encounters an empty leaf node, the data structure continues traversing unless empirically determined conditions stipulate that the process halts until the next data segment insertion before continuing.

Abstract: The present invention provides an interpreter with reduced memory access and improved jump-through-register handling. In one embodiment, a method includes storing a handler for a bytecode in a cell of a predetermined size of a table, and generating an address of the handler for the bytecode using a shift and an ADD operation. In particular, the handler address is generated by adding a base address of the table and an offset into the table. In another embodiment, a method includes prefetching a target handler address for providing improved jump-through-register handling.

Abstract: The present invention provides an improved interpreter for stack-based languages. In one embodiment, a method includes executing a first interpreter for a first state, and executing a second interpreter for a second state. In particular, the first state indicates that no elements of a stack are stored in registers of a microprocessor, and a second state indicates that an element of the stack is stored in a register of the microprocessor.

Abstract: In a system for dynamically linking a compiled procedure to referenced object components during execution of the compiled procedure, a native code loader loads the compiled procedure into a user's address space, and replaces a first instruction in the compiled procedure that references a first object component with a replacement instruction that invokes execution of a dynamic resolution procedure. While executing the compiled procedure, execution of the replacement instruction invokes execution of the dynamic resolution procedure. The dynamic resolution procedure locates the first object component, replaces the replacement instruction in the compiled procedure with a patch instruction, corresponding to the first instruction, that references the located first object component.

Abstract: In its various embodiments, the present invention provides a method and apparatus for creating a target executable program from the source code of a target computer program for execution on a target processor. The target processor provided by the method and apparatus has a first set of registers and a second set of registers. Generally, the target processor is capable of executing a first set of instructions which only address the first set of registers. The method and apparatus provides a second set of instruction for the target processor which include a subset of frequently executed instructions within the first set of instructions. These second set of instructions are novel because they able to address both the first set of registers and the second set of registers. A compiler is provided and used for compiling the source code into a number of target executable instructions and allocating the registers on the target processor.

Abstract: An optimizing compiler process and apparatus is disclosed for more accurately and efficiently identifying live variable sets in a portion of a target computer program, so as to more efficiently allocate registers in a computer central processing unit. The process of the invention includes the steps of performing a static single assignment transform to a computer program, including the addition of phi functions to a control flow graph. Basic blocks representing a use of a variable are further added to the control flow graph between the phi functions and definitions of the variables converging at the phi functions. A backward dataflow analysis is then performed to identify the live variable sets. The variables in the argument of phi functions are not included as a use of those variables in this dataflow analysis. The dataflow analysis may be iteratively performed until the live variable sets remain constant between iterations.