Patents by Inventor Daniel E. Klausmeier
Daniel E. Klausmeier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7672301Abstract: A distribution stage is disclosed comprising a plurality of inputs coupled to a plurality of first stage switching devices, a plurality of outputs coupled to a plurality of second stage switching devices, and a distribution configuration. The distribution configuration is configured to receive a plurality of bandwidth units (BU's) from each first stage switching device, and to distribute at least one BU from each first stage switching device to each second stage switching device, such that each second stage switching device is assured of receiving at least one BU from each first stage switching device. In effect, the distribution stage ensures that each first stage switching device has a logical link to each second stage switching device. In one embodiment, the distribution stage is configured in accordance with a distribution configuration that is static.Type: GrantFiled: May 2, 2003Date of Patent: March 2, 2010Assignee: Ciena CorporationInventors: Daniel E. Klausmeier, Edward Sprague
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Patent number: 7184432Abstract: A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i.e., the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix.Type: GrantFiled: November 12, 2003Date of Patent: February 27, 2007Assignee: CIENA CorporationInventors: Joel F. Adam, Darren Engelkemier, Daniel E. Klausmeier
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Patent number: 7020135Abstract: A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logically configured into a logical configuration of a power of 2. The third stages includes a plurality of switch circuits.Type: GrantFiled: December 17, 2001Date of Patent: March 28, 2006Assignee: CIENA CorporationInventors: Daniel E. Klausmeier, Jeffrey T. Gullicksen
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Patent number: 7016357Abstract: Switch frames are arbitrarily concatenated to allow for any available time slots to be used for carrying concatenated switch frames. Methods and apparatus transport switch frames in available time slots, and keep track of which time slots correspond to a group of concatenated switch frames. The switch frames are transported through the switch and synchronized on the outgoing side of the switch so that arbitrarily concatenated switch frames are synchronized with each other.Type: GrantFiled: October 26, 1999Date of Patent: March 21, 2006Assignee: CIENA CorporationInventors: Tom Q. Wellbaum, Daniel E. Klausmeier
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Publication number: 20040095025Abstract: A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routes each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i.e., the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix.Type: ApplicationFiled: November 12, 2003Publication date: May 20, 2004Applicant: CIENA CorporationInventors: Joel F. Adam, Darren S. Engelkemier, Daniel E. Klausmeier
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Patent number: 6714537Abstract: A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i.e., the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix.Type: GrantFiled: October 19, 1999Date of Patent: March 30, 2004Assignee: Ciena Corp.Inventors: Joel F. Adam, Darren Engelkemier, Daniel E. Klausmeier
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Patent number: 6535484Abstract: A method of managing oversubscription of a common buffer resource shared by a number of traffic flows in a cell switching network in response to the utilization of the common buffer resource. A buffer utilization threshold is established for each of the traffic flows. As new cells arrive, the global usage of the buffer resource is monitored. As the buffer utilization increases, the thresholds for each of the traffic flows are dynamically adjusted based upon the global usage of the buffer. Aggressive buffer allocations are scaled back when necessary, thereby leaving space for traffic flows which are relatively empty. In one embodiment, the thresholds are coded in mantissa and exponent form so that the scaling is accomplished by adjusting the exponent value.Type: GrantFiled: January 24, 2000Date of Patent: March 18, 2003Assignee: Cisco Technology, Inc.Inventors: David A. Hughes, Daniel E. Klausmeier
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Patent number: 6487202Abstract: A method of executing a sequence of multiple dependent operations, each operation including a memory read and a memory write involves overlapping memory accesses of the operations by grouping together memory reads and memory writes of multiple operations and preserving a desired sequence of the operations using a circuit external to a memory through which the memory accesses are performed. The operations may be updates to one or more linked lists. In one embodiment, the step of overlapping memory accesses may be performed by grouping together memory accesses according to ATM cell arrivals or departures. In this embodiment, the operations are associated with ATM cell arrivals or departures and may be gets or puts. Each get and put operation may be characterized by a number of atomic memory operations to update one or more linked lists.Type: GrantFiled: June 30, 1997Date of Patent: November 26, 2002Assignee: Cisco Technology, Inc.Inventors: Daniel E. Klausmeier, Kevin Wong
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Patent number: 6483854Abstract: A plurality of cells are received from a digital network and stored in a logical queue. The cells contain data information and logical connection information and the logical queue corresponds to the logical connection identified by the logical connection information. The cells are combined into a frame by extracting the cells from the logical queue and storing the cells to a local memory so that the data information is preserved. Extraction may be accomplished by notifying a local processor that the frame's worth of data is ready and then transferring the data information of the cells to a local memory at the direction of the local processor. During the transfer, error detection operations may be performed. Information may be transmitted into the digital network by segmenting a frame of data into a plurality of cells and injecting each of the cells into a logical queue. The logical queue may be constructed with a series of linked list pointers associated with the memory locations.Type: GrantFiled: January 30, 2001Date of Patent: November 19, 2002Inventors: Daniel E. Klausmeier, Kevin Wong, David A. Hughes
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Patent number: 6430191Abstract: In a digital switch, incoming cells are placed into a queue in a cell memory. The switch maintains various cell queues, including VC queues that correspond to individual connections and QBin queues that correspond to various classes of service. Cells may arrive to a VC queue or a QBin queue but will depart from a QBin queue. Accordingly, cells may be moved from VC queues to QBin queues. Cells are serviced according to the use of QBin Groups. A QBin Group (QBG) includes a number of logical queues (QBins) of cells to be transported in the digital network. After a QBG is selected, one of its logical queues is selected for servicing. The QBG may be selected by examining all of the QBGs to find an eligible QBG which is most overdue for service. A QBin of the selected QBG may then be selected by examining each of the QBins comprising the selected QBG to find the most overdue for service. The QBGs may correspond to virtual interfaces.Type: GrantFiled: June 30, 1997Date of Patent: August 6, 2002Assignee: Cisco Technology, Inc.Inventors: Daniel E. Klausmeier, Kevin Wong, Quang Nguyen, Cherng-Ren Sue, David A. Hughes, Ross Suydam Heitkamp, Rafael Gomez
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Publication number: 20020051446Abstract: The present invention utilizes a combination of time division and space switching to logically create 2n center stage switching circuits in a switch reconfigurable based on the Looping Algorithm, even though the switch includes a non-power of 2 number of center stage physical switches.Type: ApplicationFiled: December 17, 2001Publication date: May 2, 2002Inventors: Daniel E. Klausmeier, Jeffrey T. Gullicksen
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Patent number: 6343075Abstract: A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logically configured into a logical configuration of a power of 2. The third stages includes a plurality of switch circuits.Type: GrantFiled: October 26, 1999Date of Patent: January 29, 2002Assignee: CIENA CorporationInventors: Daniel E. Klausmeier, Jeffrey T. Gullicksen
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Patent number: 6201813Abstract: A plurality of cells are received from a digital network and stored in a logical queue. The cells contain data information and logical connection information and the logical queue corresponds to the logical connection identified by the logical connection information. The cells are combined into a frame by extracting the cells from the logical queue and storing the cells to a local memory so that the data information is preserved. Extraction may be accomplished by notifying a local processor that the frame's worth of data is ready and then transferring the data information of the cells to a local memory at the direction of the local processor. During the transfer, error detection operations may be performed. Information may be transmitted into the digital network by segmenting a frame of data into a plurality of cells and injecting each of the cells into a logical queue. The logical queue may be constructed with a series of linked list pointers associated with the memory locations.Type: GrantFiled: June 30, 1997Date of Patent: March 13, 2001Assignee: Cisco Technology, Inc.Inventors: Daniel E. Klausmeier, Kevin Wong, David A. Hughes
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Patent number: 6034945Abstract: A method of managing oversubscription of a common buffer resource shared by a number of traffic flows in a cell switching network in response to the utilization of the common buffer resource. A buffer utilization threshold is established for each of the traffic flows. As new cells arrive, the global usage of the buffer resource is monitored. As the buffer utilization increases, the thresholds for each of the traffic flows are dynamically adjusted based upon the global usage of the buffer. Aggressive buffer allocations are scaled back when necessary, thereby leaving space for traffic flows which are relatively empty. In one embodiment, the thresholds are coded in mantissa and exponent form so that the scaling is accomplished by adjusting the exponent value.Type: GrantFiled: May 15, 1996Date of Patent: March 7, 2000Assignee: Cisco Technology, Inc.Inventors: David A. Hughes, Daniel E. Klausmeier
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Patent number: 5838915Abstract: A method and apparatus for buffering information in a digital network are provided. Each data element arrives on a particular logical connection. The apparatus stores the data element in the tail of a queue that corresponds to the connection on which the data element arrived. The apparatus maintains one queue for each connection. The apparatus tracks the state of the queues using linked lists. Each entry in the linked list corresponds to a block in the memory used to store the data. The entries that correspond to blocks that contain data for a particular connection are linked together to reflect the order of arrival of the data stored in the corresponding blocks. Information that is generated about a particular data element after the data element has been stored is placed in the linked list entry that corresponds to the block in which the data was stored, rather than in the block with the data.Type: GrantFiled: November 17, 1997Date of Patent: November 17, 1998Assignee: Cisco Technology, Inc.Inventors: Daniel E. Klausmeier, Satish P. Sathe
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Patent number: 5835494Abstract: A method and apparatus are provided for scheduling when each of a plurality of virtual connections supported by a transmit device will be serviced by the transmit device. The transmit device includes a transmission control unit that uses a plurality of calendars to schedule when each of the plurality of virtual connections will be serviced. Virtual connections with faster transfer rates are scheduled using higher granularity calendars, while virtual connections with slower transfer rates are scheduled using lower granularity calendars. Each entry in the calendars is associated with a time interval ("cell slot") during which the transmit device is able to service one virtual connection. During a given cell slot, linked lists associated with the calendar entries that correspond to the cell slot are added to a service queue, and the virtual connection at the head of the service queue is serviced.Type: GrantFiled: March 27, 1997Date of Patent: November 10, 1998Assignee: Cisco Technology, Inc.Inventors: David A. Hughes, Daniel E. Klausmeier
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Patent number: 5666353Abstract: A frame based traffic policing system that determines if incoming data cells are conforming or non-conforming according to the a traffic contract. The frame based traffic policing system first detects a cell at the beginning or end of a frame and determines if the frame conforms with a traffic contract. If the cell does not exceed the parameters of the traffic contract, then the frame based traffic policing system deems the cell as conforming. If the cell was the first cell of a frame, then frame based traffic policing system treats all the remaining cells in the frame as conforming or non-conforming depending upon if the first data cell was conforming or non-conforming. If the cell was the last cell of a frame, then frame based traffic policing system treats all the cells of the following frame as conforming or non-conforming depending upon if the last cell of a previous frame was conforming or non-conforming.Type: GrantFiled: March 21, 1995Date of Patent: September 9, 1997Assignee: Cisco Systems, Inc.Inventors: Daniel E. Klausmeier, Charles M. Corbalis, Kambiz Hooshmand
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Patent number: 5570360Abstract: To simplify the service decision made in a queue based digital switch, a method and apparatus is introduced that makes service decisions based upon the history of incoming cells. The apparatus includes a minimum service rate circuit that monitors the rate of arriving cells. The minimum service rate circuit tests the arriving cells to determine if they are in conformance with the minimum service rate of a service contract. The minimum service rate circuit may use a continuous state leaky bucket algorithm as specified in the CCITT Recommendation I.371 document, dated 1992, to determine if a cell is in conformance with the minimum service rate of the service contract. When a cell arrives that conforms to the minimum service rate, the minimum service rate circuit notifies the server and the server serves the queue associated with the connection.Type: GrantFiled: March 20, 1995Date of Patent: October 29, 1996Assignee: Stratacom, Inc.Inventors: Daniel E. Klausmeier, Charles M. Corbalis
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Patent number: 5561663Abstract: A method for performing rate control for digital communication systems. A server serves N connection queues where each connection queue has accumulation rate a.sub.i. Each credit accumulation rate a.sub.i is divided into a set of binary coefficients. The connections are then divided into connection groups wherein each connection group has group accumulation rate created using the binary coefficients. The connection group accumulation rate is used to maintain a group credit balance c.sub.j. To select a connection to be served, the server examines the group credit balances and selects the group with the greatest credit balance. A connection within the selected group is chosen using a round-robin system. Thus the server selects a connection to serve without performing a linear scan over all the connections.Type: GrantFiled: December 30, 1994Date of Patent: October 1, 1996Assignee: Stratacom, Inc.Inventor: Daniel E. Klausmeier