Patents by Inventor Daniel E. Shier

Daniel E. Shier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Design and assembly methodology for reducing bridging in bonding electronic components to pads connected to vias
    Patent number: 6622905
    Abstract: An apparatus, comprising a substrate having a surface, comprising one or more solder pads, each having a center and connected to a via, each via having a center; positioned relative to the surface such that at least one of the one or more solder pad centers is offset from the connecting via center and an area of the at least one of the one or more solder pads overlaps an area of the connecting via.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: September 23, 2003
    Assignee: Intel Corporation
    Inventors: Daniel E. Shier, Phil Geng, Scott N. Dixon
  • Design and assembly methodology for reducing bridging in bonding electronic components to pads connected to vias
    Publication number: 20020084312
    Abstract: An apparatus, comprising a substrate having a surface, comprising one or more solder pads, each having a center and connected to a via, each via having a center; positioned relative to the surface such that at least one of the one or more solder pad centers is offset from the connecting via center and an area of the at least one of the one or more solder pads overlaps an area of the connecting via.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Daniel E. Shier, Phil Geng, Scott N. Dixon