Patents by Inventor Daniel Eaton

Daniel Eaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11989050
    Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: May 21, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Deepesh John
  • Patent number: 11947833
    Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Tsun Ho Liu
  • Patent number: 11875875
    Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: January 16, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
  • Publication number: 20230409232
    Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Tsun Ho Liu
  • Publication number: 20230206973
    Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
  • Publication number: 20230207038
    Abstract: Methods and systems are disclosed for training, by a sequencer of a memory interface system, an interface with DRAM. Techniques disclosed comprise scheduling a command sequence, including DRAM commands that are interleaved with one or more CSR commands; executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through an internal datapath of the system and the CSR commands are sent to the internal datapath; and training the interface based on exchange of data, carried out by the DRAM commands, including adjustments to an operational parameter associated with the interface.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
  • Publication number: 20230205252
    Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Deepesh John
  • Publication number: 20230205433
    Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
  • Publication number: 20230197123
    Abstract: A method and apparatus for performing a simulated write in a computer system includes, responsive to a scheduled memory operation determined by a memory controller, sending a simulated write operation to a physical layer circuitry (PHY) to increase circuit power without enabling the output of the PHY until the memory operation begins. Responsive to the memory operation being complete, sending a simulated write operation to the PHY to decrease circuit power.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Pouya Najafi Ashtiani, Craig Daniel Eaton, Kedarnath Balakrishnan
  • Publication number: 20200097421
    Abstract: According to one general aspect, an apparatus may include a processor coupled with a memory controller via a first path and a second path. The first path may traverse a coherent interconnect that couples the memory controller with a plurality of processors, including the processor. The second path may bypass the coherent interconnect and has a lower latency than the first path. The processor may be configured to send a memory access request to the memory controller and wherein the memory access request includes a path request to employ either the first path or the second path. The apparatus may include the memory controller configured to fulfill the memory access request and, based at least in part upon the path request, send at least part of the results of the memory access to the processor via either the first path or the second path.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 26, 2020
    Inventors: Hien LE, Vikas Kumar SINHA, Craig Daniel EATON, Anushkumar RENGARAJAN, Matthew Derrick GARRETT
  • Publication number: 20180300768
    Abstract: Example techniques may include: receiving information from a content provider; generating a bidding strategy based on the information, where the bidding strategy indicates a percentage of first content to be presented at a specified location on a computing device display; generating an initial bid for the one or more criteria associated with the first content in a content auction based on performance of second content that has one or more attributes in common with the first content, where the initial bid includes a monetary amount to pay in the content auction for an action relating to the first content; determining performance metrics for the one or more criteria and the initial bid based on results of the content auction; and automatically determining a revised bid for the one or more criteria based on the performance metrics and the bidding strategy.
    Type: Application
    Filed: May 10, 2018
    Publication date: October 18, 2018
    Inventors: Adam Samet, Wilfred M. Yeung, Diogo V. Andrade, Daniel Eaton, Yuriy Znovyak, William E. Walsh, Babu Rao Kashyap Kolipaka
  • Publication number: 20070161061
    Abstract: The present invention relates to compositions containing a novel protein and methods of using those compositions for the diagnosis and treatment of immune related diseases.
    Type: Application
    Filed: November 7, 2006
    Publication date: July 12, 2007
    Applicant: Genentech, Inc.
    Inventors: Hilary Clark, Daniel Eaton, Austin Gurney, Bernd Wranik
  • Patent number: 7058439
    Abstract: A breast prosthesis may be formed by forming an outer layer on a mold, and filling the mold with a polymerizable foaming composition. The mold may be formed by forming a computer model of the prosthesis based on scanning a patient. The computer model may be used to form a solid model. A prosthesis may be coupled to the patient by coupling at least one metallic insert to the prosthesis and at least one magnet to the patient. Alternately, the prosthesis may be formed with a retaining harness integral to the prosthesis. In still another method, the prosthesis may be coupled to a retaining device surgically implanted in the patient.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: June 6, 2006
    Assignee: ContourMed, Inc.
    Inventors: L. Daniel Eaton, John J. Miller, John L. May
  • Publication number: 20050272118
    Abstract: The present invention relates to compositions containing a novel protein and methods of using those compositions for the diagnosis and treatment of immune related disease
    Type: Application
    Filed: November 12, 2004
    Publication date: December 8, 2005
    Inventors: Hilary Clark, Daniel Eaton, Bernd Wranik, Wenjun Ouyang, Lino Gonzales, Kelly Loyet
  • Publication number: 20050262218
    Abstract: A method of assigning IP addresses to a plurality of managed servers coupled is provided. A set of address correlations is stored, at least temporarily, at a management server coupled to the managed servers. Each address correlation comprises a correlation between one of a plurality of geographic identifiers and one of a plurality of IP addresses. Each geographic identifier identifies a possible physical location of a managed server. A geographic identifier at least partially identifying the physical location of the managed server is received at the management server from a particular managed server. The IP address corresponding to the received geographic identifier is determined from the set of address correlations and assigned to the particular managed server.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 24, 2005
    Inventors: Gabriel Cox, Daniel Eaton, Jonathan Nalley, Stephen Rousset
  • Publication number: 20050195075
    Abstract: A system for displaying chassis component information includes a chassis and a plurality of server blades each coupled to the chassis. Each server blade comprises a respective liquid crystal display (LCD) positioned upon the server blade. The respective LCD is operable to display chassis component information.
    Type: Application
    Filed: January 8, 2004
    Publication date: September 8, 2005
    Inventors: Montgomery McGraw, Robert McClung, Gabriel Cox, Daniel Eaton, Jonathan Nalley
  • Publication number: 20030208269
    Abstract: A breast prosthesis may be formed by forming an outer layer on a mold, and filling the mold with a polymerizable foaming composition. The mold may be formed by forming a computer model of the prosthesis based on scanning a patient. The computer model may be used to form a solid model. A prosthesis may be coupled to the patient by coupling at least one metallic insert to the prosthesis and at least one magnet to the patient. Alternately, the prosthesis may be formed with a retaining harness integral to the prosthesis. In still another method, the prosthesis may be coupled to a retaining device surgically implanted in the patient.
    Type: Application
    Filed: May 3, 2002
    Publication date: November 6, 2003
    Inventors: L. Daniel Eaton, John J. Miller, John L. May
  • Patent number: 6520989
    Abstract: A flexible external prosthesis formed by first creating a thin walled hollow elastomeric shell of the shape required for anatomical augmentation. The interior of the hollow shell is filled with a flexible foam body formed into the same shape. The foam is formed by either of two methods. In one method the same mold used to form the thin walled hollow shell is used again to shape the foam into the same shape as the hollow shell. The hollow prosthesis may then be opened, the foam body inserted and the shell resealed. In another method, the foam is injected into the hollow shell while it is contained in the mold. The foam is desirably a two-part material which chemically generates a foaming agent when the two parts are mixed together. The foam then expands into the interior of the hollow shell and assumes the shape imposed by the mold. The foam body is lubricated to ensure free movement of the shell with respect to the foam body, desirably using a triglyceride oil, such as soy bean oil.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: February 18, 2003
    Assignee: Board of Trustees of the University of Arkansas
    Inventor: L. Daniel Eaton
  • Patent number: 6315796
    Abstract: A flexible, seamless tissue expanding implant with predetermined memory shape to augment tissue for accurate anatomical restoration for alloplastic reconstruction. The implant is a hollow shape formed from a material that tends to resume its molded shape even when collapsed and when reinflated resumes the desired shape. A minimal incision is made in the patient. From the incision a pocket is formed under the skin of the patient. The pocket is sized to hold the implant, which is inserted, in a collapsed deflated condition. The incision is then closed and allowed to heal. The implant is provided with a one-way, self-sealing valve for periodic inflation. The one-way valve is a latex plug encapsulated with silastic and incorporated into the implant. The valve can be palpated by the surgeon so that inflation can be performed with the implant in place by inserting a hypodermic needle through the skin of the patient, through the valve and into the interior of the implant.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: November 13, 2001
    Assignee: Board of Trustees of the University of Arkansas
    Inventor: L. Daniel Eaton
  • Patent number: RE40487
    Abstract: A method for forming the outer surface of a breast prosthesis is disclosed. A digital, three-dimensional image is formed of a patient's breast using a computerized scanner. A computer-controlled milling machine utilizes the image to form a solid model of the breast. A sheet of flexible, moldable material having a uniform, precise thickness is then vacuum-formed over the breast model. A hard, two-piece mold is cast from the flexible sheet. A soft, curable material is then either poured or injected between the two pieces of the mold to form the breast prosthesis outer surface. The breast prosthesis outer surface is then turned inside out to form a shape that is a mirror image of the patient's breast.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: September 9, 2008
    Assignee: Board of Trustees of the University of Arkansas
    Inventor: L. Daniel Eaton