Abstract: A random access memory includes a memory array of storage cells arranged in addressable rows and columns. A serial register is coupled to the memory array and to a serial register address decoder. A serial counter generates and applies to the serial register address decoder a sequence of addresses starting with an initial tap address. In response to the initial tap address, a first data bit is read out of an addressed storage cell of the memory array and is applied to a first input of a multiplexer. The initial tap address either is passed to the serial register address decoder or is incremented and applied to the serial register addressed decoder for accessing a second data bit from the serial register to a multiplexer. The initial tap address is incremented before passage only if the least significant bit of the initial address is odd.

Abstract: A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e.

Abstract: A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e.

Abstract: A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e.

Abstract: A redundant column circuit includes a row shared predecoder (12) and predecoders (16), (18) and (20). The predecoders (16-20) are input to a one-of-sixty-four decoder (28) for providing sixty-four decoded outputs therefrom, each of which is input to a one-of-four multiplexer (30). Each of the multiplexers (30) selects one of four normal decode outputs and one of four redundant decode outputs. The selected decode output is determined by the four outputs from the row shared predecoder (12). A switch bank (32) of single pole double throw switches selects between a normal and a redundant output with the redundant output having the address associated therewith incremented by one. The output of the switches in the bank (32) is input to the deactivation circuits (36) for output therefrom to a memory array (38). The memory array (38) has a redundant column (R) in parallel therewith which is controlled by the first switch in the switch bank (32).

Abstract: A redundant column circuit includes a row shared predecoder (12) and predecoders (16), (18) and (20). The predecoders (16-20) are input to a one-of-sixty-four decoder (28) for providing sixty-four decoded outputs therefrom, each of which is input to a one-of-four multiplexer (30). Each of the multiplexers (30) selects one of four normal decode outputs and one of four redundant decode outputs. The selected decode output is determined by the four outputs from the row shared predecoder (12). A switch bank (32) of single pole double throw switches selects between a normal and a redundant output with the redundant output having the address associated therewith incremented by one. The output of the switches in the bank (32) is input to the deactivation circuits (36) for output therefrom to a memory array (38). The memory array (38) has a redundant column (R) in parallel therewith which is controlled by the first switch in a the switch bank (32).