Patents by Inventor DANIEL F. YANNETTE
DANIEL F. YANNETTE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11526646Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.Type: GrantFiled: November 13, 2020Date of Patent: December 13, 2022Assignee: CHAOLOGIX, INC.Inventors: Subbayya Chowdary Yanamadala, Daniel F. Yannette, Brent Arnold Myers
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Publication number: 20210064809Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Inventors: Subbayya Chowdary YANAMADALA, Daniel F. YANNETTE, Brent Arnold MYERS
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Patent number: 10860771Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.Type: GrantFiled: February 7, 2017Date of Patent: December 8, 2020Assignee: CHAOLOGIX, INC.Inventors: Subbayya Chowdary Yanamadala, Daniel F. Yannette, Brent Arnold Myers
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Patent number: 10756710Abstract: A clock generator includes a series of inverting stages; and at least one combinational logic stage. The series of inverting stages is tapped at two or more locations along the series of inverting stages to provide intermediary outputs. A combinational logic stage of the at least one combinational logic stage is coupled to receive two or more of the intermediary outputs and generate a clock signal. Multi-phase, multi-duty cycle, non-overlapping clock signals can be generated by the clock generator based on different combinations of intermediary outputs. The clock signals can be provided to a switching network.Type: GrantFiled: April 11, 2018Date of Patent: August 25, 2020Assignee: CHAOLOGIX, INC.Inventors: Timothy Arthur Bell, Daniel F. Yannette
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Publication number: 20190042688Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.Type: ApplicationFiled: February 7, 2017Publication date: February 7, 2019Inventors: Subbayya Chowdary YANAMADALA, Daniel F. YANNETTE, Brent Arnold MYERS
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Publication number: 20180294801Abstract: A clock generator includes a series of inverting stages; and at least one combinational logic stage. The series of inverting stages is tapped at two or more locations along the series of inverting stages to provide intermediary outputs. A combinational logic stage of the at least one combinational logic stage is coupled to receive two or more of the intermediary outputs and generate a clock signal. Multi-phase, multi-duty cycle, non-overlapping clock signals can be generated by the clock generator based on different combinations of intermediary outputs. The clock signals can be provided to a switching network.Type: ApplicationFiled: April 11, 2018Publication date: October 11, 2018Inventors: Timothy Arthur BELL, Daniel F. YANNETTE
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Patent number: 9430678Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: September 9, 2015Date of Patent: August 30, 2016Assignee: CHAOLOGIX, INC.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Publication number: 20150379309Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: ApplicationFiled: September 9, 2015Publication date: December 31, 2015Inventors: Daniel F. YANNETTE, Brent Arnold MYERS
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Patent number: 9154132Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: November 7, 2014Date of Patent: October 6, 2015Assignee: CHAOLOGIX, INC.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Publication number: 20150130505Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: ApplicationFiled: November 7, 2014Publication date: May 14, 2015Inventors: DANIEL F. YANNETTE, BRENT ARNOLD MYERS
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Patent number: 8912814Abstract: Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: May 31, 2013Date of Patent: December 16, 2014Assignee: Chaologix, Inc.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Patent number: 8912816Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: February 19, 2014Date of Patent: December 16, 2014Assignee: Chaologix, Inc.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Publication number: 20140167837Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: ApplicationFiled: February 19, 2014Publication date: June 19, 2014Applicant: Chaologix, Inc.Inventors: DANIEL F. YANNETTE, BRENT ARNOLD MYERS
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Publication number: 20140132337Abstract: Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: ApplicationFiled: May 31, 2013Publication date: May 15, 2014Applicant: CHAOLOGIX, INC.Inventors: DANIEL F. YANNETTE, BRENT ARNOLD MYERS