Patents by Inventor Daniel Faken
Daniel Faken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230409775Abstract: Embodiments of the present invention provide the ability to perform deformation and stress analysis modeling in a virtual fabrication environment. More particularly, embodiments enable the virtual fabrication environment to model deformation and stress analysis directly from a voxel-based model without requiring generation of an interface conforming mesh. Stress fields for semiconductor device structures may be determined at designated points in the process sequence used to fabricate the semiconductor device.Type: ApplicationFiled: October 14, 2021Publication date: December 21, 2023Inventors: Gonzalo Feijoo, Yiguang Yan, Daniel Faken, Kenneth B. Greiner
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Patent number: 11630937Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: GrantFiled: June 23, 2021Date of Patent: April 18, 2023Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Publication number: 20210319162Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Patent number: 11074388Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: GrantFiled: March 25, 2019Date of Patent: July 27, 2021Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Patent number: 11048847Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: GrantFiled: March 1, 2019Date of Patent: June 29, 2021Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Daniel Faken, David M. Fried, Stephen R. Breit
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Publication number: 20210012049Abstract: Systems and methods for multi-material mesh generation from fill-fraction voxel model data are discussed. Voxel representations of model data are used to generate robust and accurate multi-material meshes. More particularly, a mesh generation pipeline in a virtual fabrication environment is described that robustly generates high-quality triangle surface and tetrahedral volume meshes from multi-material fill-fraction voxel data. Multi-material topology is accurately captured while preserving characteristic feature edges of the model.Type: ApplicationFiled: February 15, 2019Publication date: January 14, 2021Applicant: Coventor, Inc.Inventors: Daniel Sieger, Kenneth B. Greiner, Daniel Faken, Vincent Baudet, Stéphane Calderon
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Publication number: 20190286780Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: ApplicationFiled: March 25, 2019Publication date: September 19, 2019Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Publication number: 20190266306Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: ApplicationFiled: March 1, 2019Publication date: August 29, 2019Inventors: Kenneth B. Greiner, Daniel Faken, David M. Fried, Stephen R. Breit
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Patent number: 10242142Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: GrantFiled: March 14, 2013Date of Patent: March 26, 2019Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Stephen R. Breit, David M. Fried, Daniel Faken
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Patent number: 9659126Abstract: Improving semiconductor device fabrication by enabling the identification and modeling of pattern dependent effects of fabrication processes is discussed. In one embodiment a local mask is generated from a 3-D model of a semiconductor device structure that was created in a 3-D virtual semiconductor fabrication environment from 2-D design layout data and a fabrication process sequence. The local mask is combined with a global mask based on the original design layout data to create a combined mask. The combined mask is convolved with at least one proximity function to generate a loading map which may be used to modify the behavior of one or more processes in the process sequence. This behavior modification enables the 3-D virtual semiconductor fabrication environment to deliver more accurate 3-D models that better predict the 3-D device structure when performing the virtual semiconductor device fabrication that serves as a prelude to physical fabrication.Type: GrantFiled: January 26, 2015Date of Patent: May 23, 2017Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, David M. Fried, Mattan Kamon, Daniel Faken
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Patent number: 9317632Abstract: A virtual fabrication environment for semiconductor device structure development is discussed that enables the use of a selective epitaxy process to virtually model epitaxial growth of a crystalline material layer. The epitaxial growth occurs on a crystalline substrate surface of a virtually fabricated model device structure. A surface growth rate may be defined over possible 3D surface orientations of the virtually fabricated device structure by modeling the growth rates of the three major families of crystal planes. Growth rates along neighboring non-crystalline material may also be modeled.Type: GrantFiled: March 14, 2013Date of Patent: April 19, 2016Assignee: Coventor, Inc.Inventors: Daniel Faken, Kenneth B. Greiner, David M. Fried, Stephen R. Breit
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Publication number: 20150213176Abstract: A mechanism for identifying and modeling pattern dependent effects of processes in a 3-D Virtual Semiconductor Fabrication Environment is discussed.Type: ApplicationFiled: January 26, 2015Publication date: July 30, 2015Inventors: Kenneth B. GREINER, David M. FRIED, Mattan KAMON, Daniel FAKEN
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Patent number: 8959464Abstract: A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior.Type: GrantFiled: March 14, 2013Date of Patent: February 17, 2015Assignee: Coventor, Inc.Inventors: Kenneth B. Greiner, Daniel Faken, David M. Fried, Stephen R. Breit
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Publication number: 20140282302Abstract: A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Kenneth B. GREINER, Daniel FAKEN, David M. FRIED, Stephen R. BREIT
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Publication number: 20140282324Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: COVENTOR, INC.Inventors: Kenneth B. GREINER, Stephen R. BREIT, David M. FRIED, Daniel FAKEN
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Publication number: 20140278266Abstract: A virtual fabrication environment for semiconductor device structure development is discussed that enables the use of a selective epitaxy process to virtually model epitaxial growth of a crystalline material layer. The epitaxial growth occurs on a crystalline substrate surface of a virtually fabricated model device structure. A surface growth rate may be defined over possible 3D surface orientations of the virtually fabricated device structure by modeling the growth rates of the three major families of crystal planes. Growth rates along neighboring non-crystalline material may also be modeled.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Daniel FAKEN, Kenneth B. GREINER, David M. FRIED, Stephen R. BREIT
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Patent number: 8040345Abstract: The invention provides a system for modeling three-dimensional objects using hybrid geometric/volumetric representation, wherein sharp edges are created by a geometric representation that is connected to the volumetric representation. The system creates, maintains, and updates the hybrid representation according to user input. The system also provides for conversion of the hybrid representation into either a wholly geometric representation or a wholly volumetric representation, as may be needed for output to a given device, such as a display device, a printer, and/or a fabricating device.Type: GrantFiled: November 30, 2007Date of Patent: October 18, 2011Assignee: SensAble Technologies, Inc.Inventors: Daniel Faken, Craig Cook, Brad Amidon, Brandon Itkowitz, Scott Davidson, Vincent M. Hammer
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Publication number: 20080246761Abstract: The invention provides a system for modeling three-dimensional objects using hybrid geometric/volumetric representation, wherein sharp edges are created by a geometric representation that is connected to the volumetric representation. The system creates, maintains, and updates the hybrid representation according to user input. The system also provides for conversion of the hybrid representation into either a wholly geometric representation or a wholly volumetric representation, as may be needed for output to a given device, such as a display device, a printer, and/or a fabricating device.Type: ApplicationFiled: November 30, 2007Publication date: October 9, 2008Inventors: Daniel Faken, Craig Cook, Brad Amidon, Brandon Itkowitz, Scott Davidson, Vincent M. Hammer