Patents by Inventor Daniel Froelich

Daniel Froelich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230043022
    Abstract: A sealing ring includes: a sealing body of a rubber-elastic sealing material; and an intermediate element which is connected to the sealing body. The sealing body includes a retaining collar which delimits an undercut. The intermediate element is arranged in the undercut and assigned to the retaining collar in a non-adhered and non-destructively detachable manner.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 9, 2023
    Inventors: Erich Prem, Benjamin Kohl, Daniel Froelich
  • Publication number: 20220282791
    Abstract: A seal ring includes: a static seal seat arranged inside the seal ring in a radial direction; and two sealing lips arranged outside the seal seat in the radial direction, the two sealing lips being axial sealing lips, one sealing lip of the axial sealing lips being a radially inner first and an other sealing lip of the axial sealing lips being a radially outer second axial sealing lip, the second axial sealing lip enclosing the first axial sealing lip at a radial distance on an outer circumference. The first axial sealing lip has greater flexibility in the radial direction than the second axial sealing lip. The second axial sealing lip has a surface structure radially externally on a side facing radially away from the first axial sealing lip, which surface structure is aerodynamically active during an intended use of the seal ring, so as to swirl an air layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 8, 2022
    Inventors: Erich Prem, Daniel Froelich
  • Patent number: 10706003
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Michelle Jen, Daniel Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • Publication number: 20190303338
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Application
    Filed: February 4, 2019
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Michelle Jen, Daniel Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • Patent number: 9946683
    Abstract: Techniques for reducing precision timing message uncertainty are described herein. A method includes resetting an elastic buffer of a first device in response to a second device linked with the first device sending SKIP (SKP) ordered sets to the first device. The method also includes initiating a PTM handshake with the second device in response to resetting the elastic buffer. Additionally, the method includes sending PTM messages to the second device immediately after receiving the SKP ordered sets.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Daniel Froelich, David J. Harriman
  • Publication number: 20170235701
    Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.
    Type: Application
    Filed: December 24, 2014
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventors: Akshay Pethe, Mahesh Wagh, David Harriman, Su Wei Lim, Debendra Das Sharma, Daniel Froelich, Venkatraman Iyer, James Jaussi, Zuoguo Wu
  • Publication number: 20160188524
    Abstract: Techniques for reducing precision timing message uncertainty are described herein. A method includes resetting an elastic buffer of a first device in response to a second device linked with the first device sending SKIP (SKP) ordered sets to the first device. The method also includes initiating a PTM handshake with the second device in response to resetting the elastic buffer. Additionally, the method includes sending PTM messages to the second device immediately after receiving the SKP ordered sets.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Daniel Froelich, David J. Harriman
  • Publication number: 20160182257
    Abstract: An apparatus is described herein. The apparatus comprises a physical layer (PHY), wherein analog circuitry of the physical layer is to determine a data rate. The apparatus also comprises a media access layer (MAC), wherein the media access layer is to receive the data rate from the physical layer.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: Daniel Froelich, Zuoguo Wu, Anupriya Sriramulu