Abstract: In general, the invention is directed to techniques of scalable replication of data in persistent or volatile data storage devices. In particular, a computing device comprises a host acting as a device host for a data storage device and a plurality of data storage devices capable of persistent storage of data. A data storage replication component in the computing device acts as a data storage device. This data storage replication component comprises a device interface and a plurality of host interfaces. Each of the host interfaces acts as a device host for one or more data storage devices in the plurality of data storage devices. The primary data storage replication component may cause instructions (e.g., read, write, and control instructions) and data received from the host to be replicated on each data storage device in the plurality of data storage devices.

Abstract: In general, the invention is directed to techniques of scalable replication of data in persistent or volatile data storage devices. In particular, a computing device comprises a host acting as a device host for a data storage device and a plurality of data storage devices capable of persistent storage of data. A data storage replication component in the computing device acts as a data storage device. This data storage replication component comprises a device interface and a plurality of host interfaces. Each of the host interfaces acts as a device host for one or more data storage devices in the plurality of data storage devices. The primary data storage replication component may cause instructions (e.g., read, write, and control instructions) and data received from the host to be replicated on each data storage device in the plurality of data storage devices.

Abstract: An integrated multi-channel Fiber Channel analyzer provides coordinated and cooperative triggering and capture of data across multiple channels in a Fiber Channel network. The integrated multi-channel analyzer accommodates up to sixteen separate analyzer channels in a single cabinet. Each analyzer channel is comprised of an input port connection to the Fiber Channel network, a trace buffer memory that captures data and logic circuitry that controls the operation of the trace buffer memory in response to a status condition. A high speed status bus is connected to each analyzer channel and propagates the status conditions of each analyzer channel to all other analyzer channels. In this way, the integrated multi-channel analyzer allows for distributive control over triggering decisions across multiple analyzer channels, and also allows for multi-level triggering where different conditions may be detected by different analyzer channels.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.