Abstract: A method of forming a self-aligned contact in the fabrication of an integrated circuit is described. Semiconductor device structures are formed on a semiconductor substrate wherein their top and side surfaces are covered by a silicon nitride layer. A diagonal width of the silicon nitride layer on the side surfaces is a critical dimension. A layer of silicon oxide is deposited over the device structures and contacting the substrate adjacent to at least one of the semiconductor device structures where the self-aligned contact is to be formed. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned contact. Thereafter, the photoresist is exposed to ultraviolet light whereby the photoresist layer is cured.

Abstract: The practice of forming self-aligned contacts in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. Current etchants rely upon the formation of a polymer over nitride surfaces which enhances oxide/nitride selectivity. However, for contact widths of less than 0.35 microns, as are encountered in high density DRAMs, the amount of polymer formation required to attain a high selectivity causes the contact opening to close over with polymer before the opening is completely etched. This results in opens or unacceptably resistive contacts. On the other hand, if the etchant is adjusted to produce too little polymer, the nitride cap and sidewalls are thinned or etched through, producing gate to source/drain shorts.

Abstract: A method for providing a uniform coating of photoresist over substrate for defining high density integrated device and circuit patterns. This is accomplished by applying the photoresist onto the substrate in multiple, separate dispensing steps and leveling spins to attain the designed thickness uniformly over substrate having high topographic surfaces, thereby preserve the integrity of the critical dimension for multi-level alignments used in the fabrication of integrated devices and circuits.

Abstract: Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over-simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations.

Abstract: Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations.

Abstract: A method for manufacturing an array of dynamic random access memory (DRAM) cells having a single crown-shaped or a double crown-shaped stacked capacitors is accomplished. The method involves forming an array of device areas on a silicon substrate in which FETs for the DRAM cells are formed. After forming bit line contacts and bit line metallurgy contacting one of the two source/drain areas of each FET, a thick low melting temperature glass (BPSG) is deposited and planarized by annealing. Node capacitor contact openings are formed in the BPSG using a polysilicon sidewall method that reduces the contact size, and a thick polysilicon layer is deposited to contact the node source/drain areas of the FETs, and also provides a planar polysilicon surface. A specially designed edge phase-shift mask is then used with a positive photoresist to pattern the thick polysilicon layer and form crown-shaped bottom electrodes.

Abstract: A new method for fabricating a storage capacitor, on a dynamic random access memory (DRAM) cell, having a ring-type sidewall was accomplished. The method involves opening the self-aligned node contact to the source/drain area of the field effect transistor and forming the bottom capacitor electrode. The same photoresist mask used to open the self-aligned node contact is later used to mask and partially etch the polysilicon bottom capacitor electrode to form the ring-type sidewall on the bottom electrode. The storage capacitor is then completed by forming a thin capacitor dielectric and depositing the top electrode. The method provides a simple process that increases the capacitance of the storage capacitor by about 40 percent while not adversely affecting the leakage current.