Abstract: Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.

Abstract: A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

Abstract: Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.

Abstract: An apparatus comprises a resonator including a plurality of switched impedances spatially distributed within the resonator and a corresponding plurality of transconductance elements distributed within respective distances among the switched impedances. The resonator has a given desired resonant frequency and a given amplitude of response. Combined pairs of the switched impedances and transconductance elements have respective parasitic resonant frequencies which are higher than the given desired resonant frequency and have respective amplitudes of response which are lower than the given amplitude of response. The apparatus may be a voltage controlled oscillator or an active filter.

Abstract: Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error.

Abstract: Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio.

Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

Abstract: A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.

Abstract: Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.