Abstract: A peak detector that is particularly suitable for measuring the peak value of an RSSI-signal in a digital communication device. The peak detector includes a peak value storage capacitor which is charged by a high current or by a low current. When the RSSI-signal is greater than the output voltage of the peak detector, the storage capacitor is charged with the low current. When the RSSI-signal is substantially greater than the output voltage of the peak detector, the storage capacitor is charged with the high current. Herewith, it is achieved that the peak value of the RSSI-signal is determined quickly, without any overshoot, i.e. the peak value is determined accurately.

Abstract: A voltage reference arrangement is known for deriving a number of voltages from an input reference voltage. The known arrangement utilizes a rigid resistive voltage divider. A flexible voltage reference arrangement is provided in which inaccuracies in the input reference voltage are eliminated, and a plurality of accurate voltages can be easily derived from an obtained reference voltage. The arrangement comprises a digitally controlled potentiometer having a slider coupled to a multiplexer for multiplexing the slider to an input of a differential amplifier and to outputs. The voltage reference arrangement may be used in a voltmeter and in a battery subtractor in a telephone handset so as to share hardware.

Abstract: A wireless digital communication device having a pulse shaping network for pulse shaping digital signals before modulation. The pulse shaping network comprises a shift register to which data to be modulated are fed. Outputs of the shift register are connected to control inputs of switched weighted current sources. The switched weighted current sources are summed over an output resistor. An adjustment voltage for adjusting the magnitude of the shaped data is fed to one input of a differential amplifier, a reference resistor being coupled to another input of the amplifier, and to a reference current source which is mirrored into the switched weighted current sources. Thus, an accurate and easily adjustable pulse shaping network is obtained.

Abstract: A system comprising an output buffer circuit and an input buffer circuit in which the output buffer circuit appreciably reduces the level of the signal to be transmitted between the two buffer circuits so as to, which corresponds to U.S. Pat. No. 4,305,009, disturbing signals in the output buffer circuit. These disturbing signals occur as a result of high peak currents during voltage transitions in the input signal, after which the original level is restored in the input buffer circuit. To further reduce the effect of disturbing signals, a reference voltage level, which is largely free of disturbing signals and relative to which the output signals of the output buffer circuit are determined, is likewise transmitted to the input buffer circuit. To increase the edge steepness of the signal to be transmitted, a series combination of an inverter and a capacitive voltage divider is coupled between the input of the output buffer circuit and the input of the input buffer circuit.

Abstract: Digital filter arrangement in which a sample of an output signal is calculated by forming the sum of the products of a set of samples of an input signal and a set of filter coefficients. To provide a more accurate encoding of the filter coefficients without great consequences for the hardware, the filter coefficients are encoded by combinations of the form:K1.multidot.2.sup.m +K2.multidot.2.sup.n,wherein n and m are integers and it holds that for at least one coefficient: 1<.vertline.K1.vertline.<2 and .vertline.K2.vertline.=0 or 1 or: 1<.vertline.K1.vertline.<2 and 1<.vertline.K2.vertline.<2 and a multiplier is present for combinatorially multiplying a signal sample by the factor .vertline.K1.vertline., .vertline.K2.vertline. which is located between 1 and 2.

Abstract: A telecommunication system comprising a bus conductor to which respective stations are connected by respective transformers, communication taking place via voltage pulses V.sub.p on the bus. Each voltage pulse V.sub.p causes a magnetizing current i.sub.m to be developed in the spurious self-inductance of each connected transformer, which if not compensated will cause a faulty voltage to arise after termination of the pulse and so result in faulty information transfer. The invention provides a controllable voltage source which generates a compensating current i.sub.c in the winding of each connected transformer to compensate this faulty voltage, so that at the instants of pulse termination the total magnetization of all transformers remains unchanged.

Abstract: Data packets are transmitted over a time-division multiplex system with CSMA-CD connecting multiple stations and having a signaling channel and message-switch channels. Collisions caused by simultaneous attempts by two or more stations to access the system for transmission are limited to the signaling channel, and are remedied by a retransmission procedure in which the unique station address number determines the frame number in which retransmission may start. This procedure guarantees that a station can access a message-switched channel within a short period of time.

Abstract: Electronic telephone set having DTMF tone dialling. By some slight additions to the logic circuits of the digital DTMF tone generator this tone generator is made suitable for generating a two-tone ringing signal, for supervising the frequency of the incoming ringing voltage and for generating a tone interval of approximately 0.1 s for the call-back function.

Abstract: A transmission circuit for an electronic telephone set has a transmit circuit which as far as direct current is concerned is connected in parallel with the series arrangement of a logic circuit, a current source and a receive circuit. This enables the voltage space of the transmit circuit to be equal to the line voltage so that a maximum transmit level can be achieved.

Abstract: A line looping circuit for connection between the wires of a subscriber's line via the hook contact and in parallel with further equipment of the subscriber's set. The circuit comprises the series arrangement of the main current path of one or two field effect transistors and a resistor, the gate of each field effect transistor being connected to the end of the resistor remote from that field effect transistor. The circuit has a low resistance to small currents and a high resistance to high currents.

Abstract: Telephone subscriber's line interruption arrangement comprising a series arrangement of a semiconductor interrupter contact and a control circuit connected between a first line terminal and a second line terminal, in which a subscriber's line can be connected to the line terminals and via a hook contact. In order to ensure that at low line currents, that is to say in the case of long to very long subscriber's lines, the voltage drop across the interrupter contact is kept very low, the control circuit comprises an output circuit which ensures that the voltage at the control electrode of the semiconductor interrupter contact is at least equal to the voltage at the first terminal.

Abstract: Voltage stabilizer for use in a telephone instrument, comprising the series arrangement of the main current paths of two transistors (4, 6) and a voltage divider (8, 9) connected in parallel therewith connected between first (1) and second (2) terminals. The bases of the transistors (3, 5) are connected to the voltage divider. The transistors (3, 5) and (4, 6) are connected in the Darlington pair configuration. In addition, in order to obtain a high AC impedance, the stabilizer includes a capacitor (11) which is arranged between the bases of transistors (3, 5) and terminal (2) to which the emitter of the second transistor (6) is coupled. To reduce the switch-on time of the stabilizer, a thyristor (13, 14) is provided between the first terminal (1) and the base of the first transistor (3) and a voltage divider (17, 18) whose tap (19) is connected to the cathode gate of the thyristor circuit is connected between the first terminal (1) and the junction of the main current paths of the transistors (4, 6).

Abstract: A circuit comprising a line interruption arrangement for producing dial pulses, comprising a series arrangement of a semiconductor switching element and a control device connected between a first and a second line terminal, the first and second terminals being provided to enable connection to a subscriber's line. To limit the current in the subscriber's line while using a minimum of components, the control circuit comprises a current detection device which is connected to the control electrode of the semiconductor switching element to drive the semiconductor switching element into saturation when the line current is below a predetermined value and to drive the semiconductor switching element out of saturation when the line current is above the said predetermined value.

Abstract: Decimation non-recursive digital linear phase FIR filter having a length N and a decimation factor q, comprising a first and a second digital delay line, both consisting of a cascade arrangement of a number of auxiliary delay lines each having a time delay qT. An individual distribution line is connected to the input of each of the delay lines as well as to the output of each of the auxiliary delay lines. Digital input signal components occurring with a period T are applied to the input of the first digital delay line and each auxiliary delay line contains q of these components. These two delay lines are coupled to one another by means of a sequence reversing device which comprises a store having a capacity of q signal components. This reversing device applies, in the next control interval, q input signal components, produced in a given control interval of length qT by the first delay line, in reversed order to the second delay line.

Abstract: Voltage stabilizer for use in a telephone set which in order to obtain a low direct current resistance and a high alternating current impedance comprises two series-arranged transistor circuits connected between two terminals and a voltage divider connected between the terminals, the bases of the transistor circuits being connected to the terminals and the base of the upper transistor circuit of a capacitor being connected to the terminal to which the emitter of the lower transistor circuit has been coupled.