Abstract: A fractional-N frequency synthesizer has a VCO with an output for supplying an output signal of a particular frequency, and an input for receipt of a control signal for controlling the operation of the VCO so that it locks in on a reference frequency. Compensation circuitry is coupled to the input for compensating the output signal for phase jitter. The compensation circuitry has a charge pump that supplies a compensation current to the input. The timing is derived from the output signal, thus rendering the compensation current independent of the frequency range of the VCO and of the reference frequency.

Abstract: A low-voltage, high-speed voltage level interface circuit for signal level translation between circuits operating at different supply voltages. The circuit utilizes a folded cascode structure with a separate reference voltage to achieve high-speed and low-voltage performance. Voltage divider circuits are provided at the signal and reference inputs.

Abstract: A new logic family is identified that achieves much better speeds than CML logic gates. This new logic family operates with multiple inputs and a single logic level, using differential pairs of transistors for each input transistor of the multiple input. This new logic family enables high speed operation, or higher speed, than the prior art, together with lower operating current and a power-delay enhancement significantly increased over the prior art.

Abstract: The tail current of a differential transistor pair (12 and 14) is controlled by a feed-back means (40) that couples the pair's tail node (16) to the control input of each transistor for controlling a biasing current through each transistor. The control input of each transistor further receives an input signal in addition to an output signal of the feed-back means. As a result, the circuit has a stable and accurate tail current, and in addition is suitable for a low-voltage supply or for high-current operation.