Patents by Inventor Daniel J. Post

Daniel J. Post has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9069695
    Abstract: Systems and methods are disclosed for correction block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 30, 2015
    Assignee: APPLE INC.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Patent number: 9069657
    Abstract: Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: June 30, 2015
    Assignee: APPLE INC.
    Inventors: Daniel J. Post, Nir Jacob Wakrat, Vadim Khmelnitsky
  • Patent number: 9063886
    Abstract: Systems and methods are provided for storing data to or reading data from a non-volatile memory (“NVM”), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, flags, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. This way, even if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: June 23, 2015
    Assignee: APPLE INC.
    Inventors: Daniel J. Post, Vadim Khmelnitsky, Nir J. Wakrat
  • Patent number: 8990614
    Abstract: Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Apple Inc.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Patent number: 8972650
    Abstract: Systems and methods are disclosed for increasing efficiency of read operations by selectively adding pages from a pagelist to a batch, such that when the batch is executed as a read operation, each page in the batch can be concurrently accessed. The pagelist can include all the pages associated a read command received, for example, from a file system. Although the pages associated with the read command may have an original read order sequence, embodiments according to this invention re-order this original read order sequence by selectively adding pages to a batch. A page is added to the batch if it does not collide with any other page already added to the batch. A page collides with another page if neither page can be accessed simultaneously. One or more batches can be constructed in this manner until the pagelist is empty.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: March 3, 2015
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Matthew Byom
  • Patent number: 8966209
    Abstract: Systems and methods are disclosed for efficient allocation policies for a system having non-volatile memory. A file system allocator of the system can be configured to allocate memory regions that are aligned with one or more logical blocks of a logical space (e.g., one or more super block-aligned regions). In some embodiments, the file system allocator can monitor the number of free sectors corresponding to each logical block. In other embodiments, the file system allocator can monitor a ratio of free space to total space corresponding to each logical block. The file system allocator can select a logical block based at least in part on the number of free sectors of the logical block. In some cases, the file system allocator can allocate the free sectors of the logical block in a sequential order.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: February 24, 2015
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Brian Sutton
  • Patent number: 8954647
    Abstract: Systems and methods are provided for storing data to or reading data from a non-volatile memory (“NVM”), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, a directional flag, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. The directional flag indicates the geometric relationship between the first memory location and the second memory location. Thus, if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 10, 2015
    Assignee: Apple Inc.
    Inventor: Daniel J. Post
  • Patent number: 8949508
    Abstract: Systems and methods are provided for handling temporary data that is stored in a non-volatile memory, such as NAND flash memory. The temporary data may include hibernation data or any other data needed for only one boot cycle of an electronic device. When storing the temporary data in one or more pages of the non-volatile memory, the electronic device can store a temporary marker as part of the metadata in at least one of the pages. This way, on the next bootup of the electronic device, the electronic device can use the temporary marker to determine that the associated page contains unneeded data. The electronic device can therefore invalidate the page and omit the page from its metadata tables.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventors: Nir J. Wakrat, Daniel J. Post
  • Patent number: 8949506
    Abstract: Systems and methods are provided for initiating wear leveling on block-aligned boundaries for non-volatile memories (“NVMs”), such as flash memory. In some embodiments, an electronic device including the NVM may suspend the programming of data upon reaching the end of a dynamic block. The electronic device may then perform wear leveling on a low-cycled block of the NVM. The electronic device may thus be configured to copy static data from the low-cycled block to another block of the NVM. After wear leveling has completed, the memory interface can program a second portion of the data to a new dynamic block of the NVM. This way, the electronic device can improve the efficiency of garbage collection. In addition, the electronic device can decrease the programming time for user generated writes, the wearing of the NVM, and overall power consumption.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Vadim Khmelnitsky
  • Patent number: 8949512
    Abstract: Systems and methods are disclosed for trim token journaling. A device can monitor the order in which trim commands and write commands are applied to an indirection system stored in a volatile memory of the device. In some embodiments, the device can directly write to a page of an NVM with a trim token that indicates that a LBA range stored in the page has been trimmed. In other embodiments, a device can add pending trim commands to a trim buffer stored in the volatile memory. Then, when the trim buffer reaches a pre-determined threshold or a particular trigger is detected, trim tokens associated with all of the trim commands stored in the trim buffer can be written to the NVM. Using these approaches, the same sequence of events that was applied to the indirection system during run-time can be applied during device boot-up.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventors: Andrew W. Vogan, Matthew J. Byom, Daniel J. Post
  • Patent number: 8935459
    Abstract: Systems and methods are disclosed for heuristics associated with programming data in a non-volatile memory (“NVM”). One or more applications can generate information that notifies a system of the amounts of recoverable and unrecoverable new data that will be programmed to an NVM. Based on this information, the system can calculate the amount of new data that needs to be placed in a bulk mode instead of a SLC mode. By utilizing multi-modal modes of an NVM effectively, the system can improve overall performance and reduce the probability of unnecessary garbage collection.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: January 13, 2015
    Assignee: Apple Inc.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Patent number: 8924632
    Abstract: Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). A tree can be stored in volatile memory that includes a logical-to-physical mapping between a logical space and physical addresses of the NVM. When the amount of memory available for the tree is below a pre-determined threshold, a system can attempt to reduce the number of data fragments in the NVM, and consequently flatten a portion of the tree. The NVM interface may select an optimal set of entries of the tree to combine. Any suitable approach can be used such as, for example, moving one or more sliding windows across the tree, expanding a sliding window when a condition has been satisfied, using a priority queue while scanning the tree, and/or maintaining a priority queue while the tree is being updated.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Vadim Khmelnitsky
  • Patent number: 8892981
    Abstract: Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface of an electronic device can program user data to a super block of the NVM. The NVM interface can then determine if a program disturb has occurred in the super block. In response to detecting that a program disturb has occurred in the super block, the NVM interface can perform garbage collection on the super block. The NVM interface can then use outer codewords associated with the super block to recover from any uncorrectable error correction code errors detected in the super block.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 18, 2014
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Kenneth Herman
  • Patent number: 8886875
    Abstract: This can relate to handling a non-volatile memory (“NVM”) operating at a substantially full memory. The non-volatile memory can report its physical capacity to an NVM driver. The NVM driver can scale-up the physical capacity a particular number of times to generate a “scaled physical capacity,” which is then reported to the file system. Because the scaled physical capacity is greater than the NVM's actual physical capacity, the file system allocates a logical space to the NVM that is substantially greater than the NVM's capacity. This can cause less crowding of the logical block addresses within the logical space, thus making it easier for the file system to operate and improving system performance. A commitment budget can also be reported to the file system that corresponds to the NVM's physical capacity, and which can define the amount of data the file system can commit for storage in the NVM.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Nir J. Wakrat
  • Patent number: 8886963
    Abstract: Systems and methods are disclosed for secure relocation of encrypted files for a system having non-volatile memory (“NVM”). A system can include an encryption module that is configured to use a temporary encryption seed (e.g., a randomly generated key and a corresponding initialization vector) to decrypt and encrypt data files in an NVM. These data files may have originally been encrypted with different encryption seeds. Using such an approach, data files can be securely relocated even if the system does not have access to the original encryption seeds. In addition, the temporary encryption seed allows the system to bypass a default key scheme.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 11, 2014
    Assignee: Apple Inc.
    Inventors: Conrad Sauerwald, Daniel J. Post, Eric Brandon Tamura, Matthew J. Byom, Puja Dilip Gupta
  • Publication number: 20140297935
    Abstract: Systems and methods are disclosed for mount-time reconciliation of data availability. During system boot-up, a non-volatile memory (“NVM”) driver can be enumerated, and an NVM driver mapping can be obtained. The NVM driver mapping can include the actual availability of LBAs in the NVM. A file system can then be mounted, and a file system allocation state can be generated. The file system allocation state can indicate the file system's view of the availability of LBAs. Subsequently, data availability reconciliation can be performed. That is, the file system allocation state and the NVM driver mapping can be overlaid and compared with one another in order to expose any discrepancies.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Inventors: Daniel J. Post, Nir Jacob Wakrat, Vadim Khmelnitsky
  • Patent number: 8850160
    Abstract: Systems and methods are disclosed for adaptive writing behavior for a system having non-volatile memory (“NVM”). A memory interface of a system can be configured to determine whether a write preference of the system is skip-sequential. In response to determining that the write preference is skip-sequential, the memory interface can sequentially program data to a first set of pages of a block of the NVM. In addition, the memory interface can sequentially pre-merge gaps between the first set of pages with one or more pages of a data block. Moreover, the memory interface can be configured to switch to an alternative programming state in response to determining that at least one condition has been satisfied. For example, the memory interface can stop programming data sequentially, and instead program data in the order that the data is received from a file system.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: September 30, 2014
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Brian Sutton
  • Publication number: 20140281687
    Abstract: Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: APPLE INC.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Publication number: 20140281588
    Abstract: Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Apple Inc.
    Inventors: Andrew W. Vogan, Matthew J. Byom, Alexander C. Sanks, Daniel J. Post, Hari Hara Kumar Maharaj, Nir Jacob Wakrat, Kenneth L. Herman
  • Publication number: 20140281179
    Abstract: Systems and methods are disclosed for stochastic block allocation for improved wear leveling for a system having non-volatile memory (“NVM”). The system can probabilistically allocate a block or super block for wear leveling based on statistics associated with the block or super block. In some embodiments, the system can select a set of blocks or super blocks based on a pre-determined threshold of a number of cycles (e.g., erase cycles and/or write cycles). The block or super block can then be selected from the set of super blocks. In other embodiments, the system can use a fully stochastic approach by selecting a block or super block based on a biased random variable. The biased random variable may be generated based in part on the number of cycles associated with each block or super block of the NVM.
    Type: Application
    Filed: June 9, 2014
    Publication date: September 18, 2014
    Applicant: Apple Inc.
    Inventors: Daniel J. Post, Nir J. Wakrat