Abstract: The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.

Abstract: The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.

Abstract: The invention provides a method of planarizing an irregular surface of a semiconductor wafer. In one embodiment, the method comprises applying a photoresist material over recessed areas and protruding areas of the irregular surface, etching the photoresist, etching partially into protruding areas of the irregular surface to remove a portion of the irregular surface, and polishing the irregular surface to a substantially planar surface. In some embodiments method may include chemically and mechanically polishing the irregular surface.

Abstract: An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.

Abstract: An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.

Abstract: Self-aligned contacts are formed to regions between closely spaced features by a method which uses differential etch rates between first and second dielectrics deposited over the closely spaced features.

Abstract: A semiconductor device including a single crystal semiconductor host material having a surface; an ultrathin pseudomorphic single crystal epitaxial interlayer formed on the surface of the host material, wherein the interlayer is formed of a material and has a thickness selected so that the material of the interlayer is elastically deformed on the surface of the host material to match the lattice constant of the interlayer material with the lattice constant of the host material; and a further material incompatible with the host material when interfaced directly with the host material, but compatible with the interlayer, provided on the interlayer and thereby interfaced with the host material to perform a predetermined function with respect to the interlayer and the host material.

Abstract: An integrated circuit design and method for its fabrication are disclosed. A bilevel-dielectric is formed to cover the active regions of a transistor and raised topographic features such as a gate runner. The upper level of the dielectric is planarized to provide for easier subsequent multilevel-conductor processing. Windows are opened in the bilayer dielectric by etching through the upper level of the dielectric, stopping on the lower level of the dielectric. Then the etch procedure is continued to etch through the lower level of the dielectric.