Abstract: Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition.

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract: A circuit including headset type detection provides compatibility with different transducer types, such as headphones provided by different manufacturers. An audio circuit that generates or receives an audio signal includes electrical terminals for coupling to a transducer device, at least one of which carries the audio signal. A transducer device type detection circuit is included and detects a type of a transducer device coupled to the audio device from characteristics measured at the multiple electrical terminals when the transducer is coupled to the audio device. The circuit also includes a configuration control circuit for altering a configuration of the audio device according to a detected type of the transducer device.

Abstract: A voltage reference circuit provides a precision voltage reference output without requiring a filter capacitor. The voltage reference output is generated by a digitally-controlled source, which has a value set by the output of a digital filter that filters the output of a comparison circuit that compares the voltage reference output to another reference. A selectable mode can be provided to provide a fast response during a startup/reset period and an optional hold or narrowband response after startup. The mode selection may also offer selection of an externally-supplied digital control value and/or a resistor divider type voltage reference as an alternative to the digitally-controlled source.

Abstract: An energy-efficient consumer device audio power output stage provides improved battery life and reduced power dissipation. A power supply having a selectable operating mode supplies the power supply rails to the power amplified output stage. The operating mode is controlled in conformity with the audio signal level, which may be determined from a volume control setting of the device and/or from a signal level detector that determines the amplitude of the signal being amplified. The power supply may be a charge pump in which the operating mode uses a capacitive divider to provide for selection of a power supply output voltage that is a rational fraction of the power supply output voltage in a full-voltage operating mode.

Abstract: A charge pump power supply for a consumer device audio power stage has an efficiency selected according to signal level. The frequency of operation of the charge pump and/or the effective size of a switching transistor bank is adjusted based upon a volume (gain) setting, or a detected signal level, so that internal power consumption of the charge pump is reduced when high output current is not required from the audio power stage and consequently from the charge pump. Operating modes of the charge pump are selected by the signal level indication and include at least a high power and a high efficiency mode selected by setting the charge pump operating frequency and/or enabling or disabling switching of one or more of multiple parallel transistors used to implement each switching element of the charge pump, thereby setting the level of gate capacitance being charged/discharged by the gate driver circuit(s).

Abstract: A charge pump power supply for an audio power amplifier integrated circuit has an operating mode selected according to an indication of operating environment and/or a process position of the integrated circuit. The operating mode selects the output voltage provided by the charge pump and may also select efficiency by selecting a frequency of operation of the charge pump and/or the effective size of a switching transistor bank. The selection is made in conformity with an indication of a process position of the integrated circuit and/or an indication of an environment of the integrated circuit, such as temperature, power supply voltage and/or load impedance values, and generally also in conformity with a volume (gain) setting, or a detected signal level, so that internal power consumption of the amplifier and charge pump is reduced when a high signal level is not being reproduced at the audio power stage.

Abstract: An energy-efficient consumer device audio power output stage provides improved battery life and reduced power dissipation. A power supply having a selectable operating mode supplies the power supply rails to the power amplified output stage. The operating mode is controlled in conformity with the audio signal level, which may be determined from a volume control setting of the device and/or from a signal level detector that determines the amplitude of the signal being amplified. The power supply may be a charge pump in which the operating mode uses a capacitive divider to provide for selection of a power supply output voltage that is a rational fraction of the power supply output voltage in a full-voltage operating mode.

Abstract: A method of sampling an input signal in a delta-sigma modulator having at least an integrator stage and a feedback digital-to-analog converter (DAC) stage includes sampling an input signal at a sampling rate by alternately utilizing the two sampling capacitors during two sampling cycles such that the two sampling capacitors are each being utilized at half the rate of the sampling rate. Samples from the two sampling capacitors are summed at the sampling rate at an intermediate node with a feedback samples provided by the feedback DAC stage at the sampling rate to generate output samples which are output from integrator stage at the sampling rate.