Abstract: A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region.

Abstract: A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor.

Abstract: An integrated circuit fabrication process is provided for forming a transistor having shallow effective source/drain regions and/or laterally shortened source/drain regions. In one embodiment a mesa is formed from the semiconductor substrate. The mesa preferably extends from an upper surface of the semiconductor substrate. A gate conductor is preferably formed on a dielectric layer which is formed on an upper surface of the mesa. LDD areas and source/drain regions are formed such that the regions are substantially contained within the mesa. In another embodiment, a gate conductor material is deposited within a trench, the trench being lined with a gate dielectric material, formed in a semiconductor substrate. The deposited gate conductor material is etched to form a gate conductor in which a lower surface of the gate conductor is substantially below an upper surface of the silicon substrate.

Abstract: An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the source region. Contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, a ground voltage may be applied to the conductor to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be applied to the conductor to bias both the source region and the well. Absent the need to form contacts to both the source region and the well-tie region and conductors to such contacts, less space is required to bias the well and the source region.

Abstract: An integrated circuit and process for making the same is provided in which a transistor including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, the gate dielectric is formed from a transition metal oxide. Preferably, the transition metal oxide is formed by oxidation of a transition metal spacer. The transition metal spacer may be reduced, prior to oxidation such that a later extent of the spacer is substantially less than a lateral extent of the gate conductor.

Abstract: A method for fabricating an integrated circuit is presented wherein a first polysilicon layer dielectrically spaced above a semiconductor substrate is provided. The semiconductor substrate contains a first active region and a second active region. A first dopant is selectively introduced into the portion of the first polysilicon layer above the second active region. A second polysilicon layer may then be formed upon the first polysilicon layer and above the first active region and the second active region. A second dopant may be selectively introduced into a portion of the second polysilicon layer above the first active region. The portion of the second polysilicon layer above the first active region and the portion of the first polysilicon layer above the first active region may be patterned to form a first gate structure within the first active region.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor.

Abstract: A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure.

Abstract: A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source.

Abstract: In an IGFET device having at least one source/drain region with a lightly-doped sub-region proximate a channel region, the source/drain regions are formed by first implanting ions with parameters to form lightly-doped source/drain regions. A high density plasma deposition provides at least one spacer having preselected characteristics. As a result of the spacer characteristics, an ion implantation with parameters to form normally-doped source/drain regions is shadowed by the spacer. A portion of the source/drain region shadowed by the spacer results in a lightly-doped source/drain sub-region proximate the channel region. According to a second embodiment of the invention, the ion implantation resulting in the lightly-doped source/drain regions is eliminated. Instead, the spacer(s) formed by the high density plasma deposition and subsequent etching process only partially shadows the ion implantation that would otherwise result in normal doping of the source/drain regions.

Abstract: An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer.

Abstract: A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed within a local trench etched into a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate and a first transistor formed on the global substrate. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric.

Abstract: A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.

Abstract: A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal.

Abstract: A semiconductor device may be fabricated using a process in which a group of transistors connected between a high and low voltage sources are formed. The transistor among the group of transistors which is used for connection to the high voltage source has non-symmetrical source and drain regions. The device, exploits low operating voltages to construct new high performance transistors.

Abstract: A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop.

Abstract: A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.