Abstract: A passive magnetic constant-force apparatus comprises a geometry and arrangement of permanent magnets, ferromagnetic components, and non-magnetic structural components. The apparatus is easily and precisely adjustable, cost-effective, with a high load capacity, and with minimal parasitic forces. The apparatus is suitable for use as a counterbalance for vertical linear motion applications and may be integrated with or attached to a linear motion stage.

Abstract: The disclosure relates to a brazing method for joining substrates, in particular where one of the substrates is difficult to wet with molten braze material. The method includes formation of a porous metal layer on a first substrate to assist wetting of the first substrate with a molten braze metal, which in turn permits joining of the first substrate with a second substrate via a braze metal later in an assembled brazed joint. Ceramic substrates can be particularly difficult to wet with molten braze metals, and the disclosed method can be used to join a ceramic substrate to another substrate. The brazed joint can be incorporated into a solid-oxide fuel cell, for example as a stack component thereof, in particular when the first substrate is a ceramic substrate and the joined substrate is a metallic substrate.

Abstract: The disclosure relates to a brazing method for joining substrates, in particular where one of the substrates is difficult to wet with molten braze material. The method includes formation of a porous metal layer on a first substrate to assist wetting of the first substrate with a molten braze metal, which in turn permits joining of the first substrate with a second substrate via a braze metal later in an assembled brazed joint. Ceramic substrates can be particularly difficult to wet with molten braze metals, and the disclosed method can be used to join a ceramic substrate to another substrate. The brazed joint can be incorporated into a solid-oxide fuel cell, for example as a stack component thereof, in particular when the first substrate is a ceramic substrate and the joined substrate is a metallic substrate.

Abstract: A passive magnetic constant-force apparatus comprises a geometry and arrangement of permanent magnets, ferromagnetic components, and non-magnetic structural components. The apparatus is easily and precisely adjustable, cost-effective, with a high load capacity, and with minimal parasitic forces. The apparatus is suitable for use as a counterbalance for vertical linear motion applications and may be integrated with or attached to a linear motion stage.

Abstract: The disclosure relates to a brazing method for joining substrates, in particular where one of the substrates is difficult to wet with molten braze material. The method includes formation of a porous metal layer on a first substrate to assist wetting of the first substrate with a molten braze metal, which in turn permits joining of the first substrate with a second substrate via a braze metal later in an assembled brazed joint. Ceramic substrates can be particularly difficult to wet with molten braze metals, and the disclosed method can be used to join a ceramic substrate to another substrate. The brazed joint can be incorporated into a solid-oxide fuel cell, for example as a stack component thereof, in particular when the first substrate is a ceramic substrate and the joined substrate is a metallic substrate.

Abstract: The disclosure relates to a brazing method for joining substrates, in particular where one of the substrates is difficult to wet with molten braze material. The method includes formation of a porous metal layer on a first substrate to assist wetting of the first substrate with a molten braze metal, which in turn permits joining of the first substrate with a second substrate via a braze metal later in an assembled brazed joint. Ceramic substrates can be particularly difficult to wet with molten braze metals, and the disclosed method can be used to join a ceramic substrate to another substrate. The brazed joint can be incorporated into a solid-oxide fuel cell, for example as a stack component thereof, in particular when the first substrate is a ceramic substrate and the joined substrate is a metallic substrate.

Abstract: A method of making a planar solid oxide fuel cell is described involving: (1) sintering at least an electrolyte layer; (2) juxtaposing one of a sintered anode or cathode layer with a metal substrate, with a bonding agent therebetween; and (3) applying heat to bond the juxtaposed anode or cathode layer to the metal substrate; where the anode and cathode layers are each sintered, together or independently, simultaneously with sintering the electrolyte layer, simultaneously with applying heat to bond the ceramic fuel cell element to the metal substrate, or in one or more separate sintering steps.

Abstract: An apparatus configured to form masonry siding products is provided. The apparatus includes a mold having a mold cavity and a plurality of retention assemblies positioned within the mold. The plurality of retention assemblies are configured to form a temporary retaining force between the retention assemblies and a nail strip as castable material enters the mold cavity.

Abstract: A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a heat sink is affixed to the integrated circuit for heat flow from the integrated circuit. The method comprises forming openings in material layers overlying the semiconductor substrate, wherein the openings are disposed proximate the device and extend to the substrate. A thermally conductive material is formed in the openings to provide a thermal path from the device to the substrate.

Abstract: A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. In some embodiments, a plurality of guard rings enclosing respective arrays of matched devices are arranged over the surface of a semiconductor wafer, spaced apart so as to be not local to one another. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, both local and global matching are achieved.

Abstract: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

Abstract: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

Abstract: An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device.

Abstract: A method of preventing formation of stringers adjacent a side of a CMOS gate stack during the deposition of mask and poly layers for the formation of a base and emitter of a bi-polar device on a CMOS integrated circuit wafer. The stringers are formed by incomplete removal of a hard mask layer over an emitter poly layer over a nitride mask layer. The method includes overetching the hard mask layer with a first etchant having a higher selectivity for the emitter poly material than for the material of the hard mask, determining an end point for the overetching step by detection of nitride in the etchant and applying a poly etchant that is selective with respect to nitride to remove any residual emitter poly.

Abstract: An actuator includes a piezoelectric stack within a housing that applies a compressive load to the stack. The housing may include a cylindrical tube closed at one end and may seal the stack against fluid pressure. The housing may be shorter than the length of the piezoelectric stack and may include resilient means for inducing elastic strain in the stack. The resilient means may include one or more slots extending around the circumference of the housing and/or a corrugated region of the housing to form a tension spring at a lower end of the housing. The tension spring may then serve to draw the stack into compression. The stack may include a plurality of layers of piezoelectric or piezoceramic material interspersed with a plurality of layers of electrically conductive material and connecting means for connecting the layers to a source of electrical power.

Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.

Abstract: A resistor formed on a material layer of a semiconductor integrated circuit and a method for forming the resistor. The resistor comprises a region of resistive material with a plurality of conductive contacts or plugs in electrical contact with and extending away from the resistive material. A first and a second interconnect line are formed overlying the plugs and in conductive contact with one or more of the plurality of plugs, such that a portion of the resistive material between the first and the second interconnect lines provides a desired resistance. According to a method of the present invention, the plurality of conductive contacts are formed using a first photolithographic mask and the first and the second interconnect lines are formed using a second photolithographic mask. The desired resistance is changed by modifying the first or the second mask such that one or more dimensions of a region of the resistive material between the first and the second interconnect lines is altered.

Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.

Abstract: A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

Abstract: A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. In some embodiments, a plurality of guard rings enclosing respective arrays of matched devices are arranged over the surface of a semiconductor wafer, spaced apart so as to be not local to one another. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, both local and global matching are achieved.