Abstract: An AC-DC voltage conversion integrate circuit that integrates all the control and protection circuits, as well as the power transistors, into a single module. Passive components, such as the transformer and capacitors, are very small, as the switching frequency is in the KHz or MHz range. Including one or more integrated switched mode power supply ICs in every wall outlet allows for providing a plurality of DC voltages from such outlets.

Abstract: An AC-DC voltage conversion integrate circuit that integrates all the control and protection circuits, as well as the power transistors, into a single module. Passive components, such as the transformer and capacitors, are very small, as the switching frequency is in the KHz or MHz range. Including one or more integrated switched mode power supply ICs in every wall outlet allows for providing a plurality of DC voltages from such outlets.

Abstract: A low current output driver for a gate array. The driver has first and second reference voltage sources, a first transistor of a first conductivity type, and a plurality of second transistors of a second conductivity type. The first transistor is connected between the first reference voltage source and the output. The second transistors are series connected between the first and second reference voltage sources. The control electrode of the first transistor is connected to a common point between two of the second transistors. At least one of the second transistors is diode connected to provide an intermediate voltage to the control electrode of the first transistor, thereby reducing the output current flow.

Abstract: An integrated circuit two transistor full wave rectifier suitable for fabrication in a CMOS, NMOS or PMOS process and characterized by a high level of integration based upon shared utilization of doped regions. In one form, the full wave rectifier is configured from two diode connected field effect transistors and two parasitic p-n junctions, all formed in a substrate region of common impurity type.

Abstract: A two mask process for forming dielectrically filled planarized trenches of arbitrary width in a semiconductor substrate, the masks being of such character that they are amenable to computerized generation. The first mask defines the active regions and subdivides the trench isolation regions into a succession of trench and plateau regions, where the widths of the trench and plateau regions fall within in a dimensional range constrained by photolithographic precision of the masks and the ability to conformally deposit dielectric material into the trenches. With the first etch mask in place, the semiconductor is anisotropically etched to formed the first trench regions. A conformal deposition of dielectric follows, and by virtue of the dimensional constraints ensures substantially void free trench dielectric and a concluding substantially planar topology of the dielectric on the substrate surface.

Abstract: In a one time programmable memory device having a memory cell, a programmable device in the memory cell having a high initial resistance, a user readable circuit for reading the condition of the programmable device, and capacitance coupled with the initial resistance and having an RC time constant therewith, a circuit and its method for non-destructively testing the programmability of the programmable device. A switch device is included in the user readable circuit and is connected to the capacitance. The switch device has a first condition for discharging the capacitance and a second condition for allowing the capacitance to charge through the programmable device. An output circuit in the user readable circuit indicates when the charge on the capacitance reaches a predetermined threshold.

Abstract: A fuse programmable ROM includes a wafer for a CMOS-type structure having an emitter, which emitter is overlain by a fuse pad of an undoped polysilicon and a conductive layer. There is a layer of barrier oxide disposed on the conductive top layer of the fuse pad and a sidewall oxide surrounding the periphery of the fuse pad both of which are overlain by the metallic electrical connection.The process of producing the fuse programmable ROM includes wide utilization of standard CMOS fabrication techniques with which are included the steps of depositing fuse material of undoped polysilicon, forming the fuse material into a fuse pad, and then making an electrical connection with the fuse pad.

Abstract: A CMOS process utilizes preferential oxidation of arsenic-doped regions and the reduced diffusivity of boron in arsenic-doped regions to eliminate photomask steps and to form self-aligned enhanced p.sup.+ and n.sup.+ contacts.