Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Abstract: Methods and corresponding systems for receiving a radio frequency signal include a receiver capable of switching operating modes and operable to receive the radio frequency signal in any of the operating modes. A metric monitor is coupled to the receiver and operable to provide a metric. A controller is responsive to the metric and operable to switch the receiver between the operating modes. The operating modes can include a zero intermediate frequency (ZIF) mode and a very low intermediate frequency (VLIF) mode. The metric can include a received signal strength indicator (RSSI) and an adjacent channel indicator. The receiver can be configured to operate in the ZIF mode in response to the RSSI value satisfying a threshold and configured to operate in the VLIF mode in response to the RSSI value failing to satisfy the threshold.

Abstract: Methods and corresponding systems for receiving a radio frequency signal include a receiver capable of switching operating modes and operable to receive the radio frequency signal in any of the operating modes. A metric monitor is coupled to the receiver and operable to provide a metric. A controller is responsive to the metric and operable to switch the receiver between the operating modes. The operating modes can include a zero intermediate frequency (ZIF) mode and a very low intermediate frequency (VLIF) mode. The metric can include a received signal strength indicator (RSSI) and an adjacent channel indicator. The receiver can be configured to operate in the ZIF mode in response to the RSSI value satisfying a threshold and configured to operate in the VLIF mode in response to the RSSI value failing to satisfy the threshold.

Abstract: A high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. IIP2 calibration of the in-phase and quadrature channels may be optimized using the isolated transconductance amplifier.

Abstract: A high performance radio frequency receiver includes a low noise amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to a current; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The in-phase and quadrature pulses have a duty cycle of 20-35%. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter.

Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Abstract: Methods and corresponding systems for receiving a radio frequency signal include a receiver capable of switching operating modes and operable to receive the radio frequency signal in any of the operating modes. A metric monitor is coupled to the receiver and operable to provide a metric. A controller is responsive to the metric and operable to switch the receiver between the operating modes. The operating modes can include a zero intermediate frequency (ZIF) mode and a very low intermediate frequency (VLIF) mode. The metric can include a received signal strength indicator (RSSI) and an adjacent channel indicator. The receiver can be configured to operate in the ZIF mode in response to the RSSI value satisfying a threshold and configured to operate in the VLIF mode in response to the RSSI value failing to satisfy the threshold.

Abstract: A high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. IIP2 calibration of the in-phase and quadrature channels may be optimized using the isolated transconductance amplifier.

Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Abstract: A high performance radio frequency receiver includes a low noise amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to a current; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The in-phase and quadrature pulses have a duty cycle of 20-35%. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter.

Abstract: A multi-band high gain mixer and quadrature signal generator allows a receiver system to receive signals at multiple frequency bands without requiring significant hardware duplication. A single mixer directly receives any of three communication frequency bands such as Universal Mobile Telecommunication System (UMTS), Personal Communication Services (PCS), Digital Communication System (DCS), and Japan and US W-CDMA 800 bands without amplification. A Serial-Parallel Interface selectably forwards RF signals within the receiver's frequency channels to the mixer for demodulation into in-phase (I) and quadrature (Q) signals at a common IF output from the multi-mode receiver. Significant power and cost advantages are attained by elimination of duplicate mixers and amplifier stages.

Abstract: A VCO circuit including a VCO, a voltage supply and a control circuit. The VCO has a supply voltage input and a gain that changes with its supply voltage. The voltage supply has an adjust input and an output coupled to the supply voltage input of the VCO. The voltage supply adjusts the voltage level of its output in response to changes of the adjust input. The control circuit has a first adjust output coupled to the adjust input of the voltage supply to adjust the gain of the VCO. The VCO may include a frequency range adjust input controlled by the control circuit so that the gain of the VCO is adjusted when the frequency range is changed. For a multi-band VCO, the gain is adjusted for different frequency bands to maintain a relatively constant gain for each frequency band.

Abstract: A switchable, dual channel frequency converter is provided. The converter includes a semiconductor body having formed as a monolithic microwave integrated circuit: a pair of input signal channels; a pair of output signal channels; and, a mixer and multiplexer means, disposed between the pair of input signal channels and the pair of output signal channels, for converting the frequency of signals fed to the pair of input signal channels to a different frequency and for directing the frequency converted signals to the pair of output signal channels selectively in accordance with a control signal. The mixer and multiplexer means includes: a pair of mixers coupled to the pair of input signal channels and a common local oscillator signal; and a multiplexer network. The mixers covert the radio frequency of the signals in the pair of input signal channels into a corresponding pair of intermediate frequency signal channels.