Abstract: A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides. Metal contacts are applied to the transparent conductive oxide.

Abstract: Back junction solar cells having improved emitter layer coverage and methods for their manufacture are disclosed. In one embodiment, a back junction solar cell includes an n-type base layer having an emitter layer formed from a first p-type doped region (e.g., formed by liquid phase epitaxial regrowth) and a second p-type doped region (e.g., formed by ion implantation) that extends beyond the first region. In various embodiments, this configuration permits the first p-type doped region to be formed with a border between it and the edges of the wafer (e.g., to prevent inadvertent shunting of the cell), while the second p-type doped region extends the emitter layer to improve emitter layer coverage. In certain embodiments, the second doped p-type region may extend to the edges of the wafer's n-type base layer.

Abstract: Solar cells and methods for fabrication thereof are provided. A method may include forming a via through at least one dielectric layer formed on a semiconductor wafer by using a laser to ablate a region of the at least one dielectric layer such that at least a portion of the surface of the semiconductor wafer is exposed by the via. The method may further include applying a self-doping metal paste to the via. The method may additionally include heating the semiconductor wafer and self-doping metal paste to a temperature sufficient to drive at least some dopant from the self-doping metal paste into the portion of the surface of the semiconductor wafer exposed by the via to form a selective emitter region and a contact overlying and self-aligned to the selective emitter region.

Abstract: A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides Metal contacts are applied to the transparent conductive oxide.

Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.

Abstract: Solar cells and methods for their manufacture are disclosed. An exemplary method may include providing a semiconductor substrate and introducing dopant atoms to a front surface of the substrate. The substrate may be annealed to drive the dopant atoms deeper in the substrate to produce a p-n junction while also forming front and back passivation layers. A reflective surface is sputtered on the back surface of the solar cell. It protects and generates hydrogen to passivate one or more substrate-passivation layer interfaces at the same time as forming an anti-reflective layer on the front surface of the substrate. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.

Abstract: Solar cells and methods for fabrication thereof are provided. A method may include forming a via through at least one dielectric layer formed on a semiconductor wafer by using a laser to ablate a region of the at least one dielectric layer such that at least a portion of the surface of the semiconductor wafer is exposed by the via. The method may further include applying a self-doping metal paste to the via. The method may additionally include heating the semiconductor wafer and self-doping metal paste to a temperature sufficient to drive at least some dopant from the self-doping metal paste into the portion of the surface of the semiconductor wafer exposed by the via to form a selective emitter region and a contact overlying and self-aligned to the selective emitter region.

Abstract: Solar cells and methods for their manufacture are disclosed. An exemplary method may include providing a semiconductor substrate and introducing dopant atoms to a front surface of the substrate. The substrate may be annealed to drive the dopant atoms deeper in the substrate to produce a p-n junction while also forming front and back passivation layers. A reflective surface is sputtered on the back surface of the solar cell. It protects and generates hydrogen to passivate one or more substrate-passivation layer interfaces at the same time as forming an anti-reflective layer on the front surface of the substrate. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.

Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.

Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.

Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.

Abstract: A method for using relatively low-cost silicon with low metal impurity concentration by adding a measured amount of dopant before and/or during silicon crystal growth so as to nearly balance, or compensate, the p-type and n-type dopants in the crystal, thereby controlling the net doping concentration within an acceptable range for manufacturing high efficiency solar cells.

Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.

Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.

Abstract: The present invention provides a system for self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. This alloy of silver and silicon is the final contact material, and is composed of eutectic proportions of silicon and silver. Under eutectic proportions there is significantly more silver than silicon in the final contact material, thereby insuring good electrical conductivity of the final contact material.

Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.

Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.

Abstract: A process for dendritic web growth is described. The process includes providing a melt, growing a dendritic web crystal from the melt, replenishing the melt during the step of growing the dendritic web crystal, and applying a magnetic field to the melt during the step of growing the dendritic web crystal. An apparatus for stabilizing dendritic web growth is also described. The apparatus includes a crucible including a feed compartment for receiving pellets to facilitate melt replenishment and a growth compartment designed to hold a melt for dendritic web growth. The apparatus further includes a magnetic field generator configured to provide a magnetic field during dendritic web growth.

Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag-Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.

Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.