Abstract: According to an aspect, virtualized weight perceptron branch prediction is provided in a processing system. A selection is performed between two or more history values at different positions of a history vector based on a virtualization map value that maps a first selected history value to a first weight of a plurality of weights, where a number of history values in the history vector is greater than a number of the weights. The first selected history value is applied to the first weight in a perceptron branch predictor to determine a first modified virtualized weight. The first modified virtualized weight is summed with a plurality of modified virtualized weights to produce a prediction direction. The prediction direction is output as a branch predictor result to control instruction fetching in a processor of the processing system.

Abstract: A method, system, and computer program product of utilizing branch prediction logic in a system that processes instructions that include a branch are described. The method includes identifying the branch as conventionally predictable or not conventionally predictable, and based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating, using a processor, the branch prediction logic to another thread of the instructions or performing, using the processor, the branch prediction and speculative execution of one or more of the instructions following the branch to obtain prediction information. Based on the performing the branch prediction and the speculative execution, the method also includes verifying a match between a branch end according to the instructions and a branch end according to the branch prediction prior to providing the prediction information to a second processor processing the instructions.

Abstract: Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction.

Abstract: Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction.

Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.

Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.

Abstract: Several implementations and a design structure for decimal multiplication that uses a BCD 4221 encoding scheme, separate accumulation of partial products, accumulation of the partial products into a final product and conversion from and to a BCD 8421 coding scheme.

Abstract: A method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.

Abstract: Several implementations and a design structure for decimal multiplication that uses a BCD 4221 encoding scheme, separate accumulation of partial products, accumulation of the partial products into a final product and conversion from and to a BCD 8421 coding scheme.

Abstract: A data processing system includes a data storage unit for storing data sets accessible to a user upon receipt of permission. The data processing system restricts access to data sets by requiring a username and then requiring a password to obtain permission for access to a data set stored in a data storage unit. The system is adapted to support use of more than one said password associated with a username; and each of those passwords associated with that username permits a distinct level of access to a particular data set, whereas other passwords can provide different levels of access to any data set assigned thereto.

Abstract: Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulus-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.

Abstract: A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided.

Abstract: A method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.

Abstract: A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided.

Abstract: A data processing system includes a data storage unit for storing data sets accessible to a user upon receipt of permission. The data processing system restricts access to data sets by requiring a username and then requiring a password to obtain permission for access to a data set stored in a data storage unit. The system is adapted to support use of more than one said password associated with a username; and each of those passwords associated with that username permits a distinct level of access to a particular data set, whereas other passwords can provide different levels of access to any data set assigned thereto.

Abstract: Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulis-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.