Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed.

Abstract: Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed.

Abstract: Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Abstract: A communications parallel bus receiver interface having N+1 data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. One of the N+1 data signals comprising a spare data signal when a failure occurs in a corresponding channel transmitting one of N parallel data signals. An input switching network is configured to receive and couple N+1 parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two or three adjacent bit receivers. A calibration device calibrates one of the two or three adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through N+1 receivers for periodic recalibration of each receiver (one at a time) while N+1 inputs are processed continuously and uninterrupted.

Abstract: Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.

Abstract: An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

Abstract: A circuit includes: a pull down circuit including a first PFET and a second PFET connected in series between a pad of a USB circuit and ground; and a pull up circuit including a first NFET and a second NFET connected in series between the pad and a supply voltage. The circuit includes: a third PFET connected to a gate of the first PFET and a gate of the second PFET; a third NFET connected to a gate of the first NFET and a gate of the second NFET; a fourth PFET connected to the first NFET and the second NFET; and a fourth NFET connected to the first PFET and the second PFET. A pad voltage has a nominal minimum and maximum. Each of the first PFET, the second PFET, the first NFET, and the second NFET has a nominal voltage less than the pad voltage nominal maximum.

Abstract: An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

Abstract: A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.

Abstract: Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.

Abstract: Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Abstract: An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

Abstract: Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.

Abstract: A communications parallel bus receiver interface having N+1 data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. One of the N+1 data signals comprising a spare data signal when a failure occurs in a corresponding channel transmitting one of N parallel data signals. An input switching network is configured to receive and couple N+1 parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two or three adjacent bit receivers. A calibration device calibrates one of the two or three adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through N+1 receivers for periodic recalibration of each receiver (one at a time) while N+1 inputs are processed continuously and uninterrupted.