Abstract: Provided are methods and compositions for providing strength and/or rigidity to lightweight materials. In certain embodiments, provided are compositions and methods for providing strength, rigidity and/or improving performance of flotation devices such as surfboards.

Abstract: A height adjustable wheel support apparatus includes an upper portion connectable to a frame of a vehicle and a lower portion that is connectable to a wheel assembly. An actuator is configured to move the upper portion between first and second positions. A spacer is movable between a storage position and a use position. In the use position the spaced is disposed between the upper and lower portions. When the upper portion is in the first position a downward facing bottom surface of the upper portion bears against a support surface on the lower portion, and when upper portion is in the second position the spacer is in the use position, between the upper and lower portions, and carries at least a portion of a load exerted by the upper portion.

Abstract: A valve device of a device of a vehicle, actuated by a pressure medium has at least one valve closing member that can be brought by a valve member into an open or a closed position with respect to a valve seat for releasing or closing a flow cross section for the pressure medium. The valve closing member is connected to the valve member by at least one Cardan joint, such that the valve closing member can pivot spatially relative to the valve member.

Abstract: A height adjustable wheel support apparatus includes an upper portion connectable to a frame of a vehicle and a lower portion that is connectable to a wheel assembly. An actuator is configured to move the upper portion between first and second positions. A spacer is movable between a storage position and a use position. In the use position the spaced is disposed between the upper and lower portions. When the upper portion is in the first position a downward facing bottom surface of the upper portion bears against a support surface on the lower portion, and when upper portion is in the second position the spacer is in the use position, between the upper and lower portions, and carries at least a portion of a load exerted by the upper portion.

Abstract: Provided are methods and compositions for providing strength and/or rigidity to lightweight materials. In certain embodiments, provided are compositions and methods for providing strength, rigidity and/or improving performance of flotation devices such as surfboards.

Abstract: An apparatus and method for integrating the delivery of data from a multiplicity of sources to a set of user electronic devices that present audio, video and digital information to the user is implemented. These devices may include conventional television displays, personal computers, and other conventional audio and video equipment. Information may be received from a multiplicity of sources which may include may include digital television via terrestrial or satellite broadcast, terrestrial analog radio, and digital data exchanged via a public network, such as the Internet. The mechanism of the present invention receives the multiplicity of data streams, processes them in accordance with each stream's formatting protocols (whether an analog stream, an MPEG Transport Stream, or TCP/IP stream, for example), including any conditional access protocols, and streams the processed data, in multiplexed transport stream to the user's presentation devices via a “fat” pipe, such as a FireWire™ bus.

Abstract: A processor-based device supports performance optimization with use of an adaptive digital element. The adaptive digital element generates probability data corresponding to a probability of a performance parameter of the processor-based device. The probability data is repeatedly compared to input data corresponding to the performance parameter and is adapted to match the input data. After a predetermined number of samples, a probability value corresponding to the probability data and stored in a counter of the adaptive digital element converges to a good estimated probability of the performance parameter. The probability value is then detected and processed, and the processor-based device is adapted in accordance with the probability value. A processor of the processor-based device also can adapt system operation when the probability value reaches a predetermined trigger value.

Abstract: A host computer system is coupled to a target computer system in a computer system debug environment and accesses selected resources. A first function executed on the host, encodes a data structure with target resource descriptor information for at least one of the selected resources. A second function accesses the selected resources in accordance with the target resource descriptor information encoded in the data structure.

Abstract: A host computer system is coupled to a target computer system for operating in a debug environment. The host computer system includes a status register which can be interrogated. A programming interface encoded in computer readable media and executable on the host computer system, provides at least one callable function that determines whether a value of a selected bit or bits of the status register have changed from a predetermined state. The called function returns to a calling function in response to the change in value of the selected bit or bits. Otherwise, the called function waits for the change in value of the bit(s). The status register can include at least one status bit that indicates a state of the target computer system and a status bit that indicates a state of the host computer system.

Abstract: A computer system includes a memory for storing instructions executable by a processor and an on-chip trace memory having a plurality of locations for storing trace information that indicates execution flow in the processor. A trace access instruction provides for access to the on-chip trace memory on the processor. The trace access instruction can be a write instruction or a read instruction. Typically, both read and write to the trace memory is provided. The system also has the capability to trace on start or restart of an executable thread by providing to the processor an indication of which executable thread to trace via a debug port. That indicates to the processor to provide trace information when the executable thread starts. When execution of the executable thread starts, the processor places an identifier corresponding to the executable thread into the trace memory to indicate that subsequent entries placed into the trace memory are part of said executable thread.

Abstract: An integrated circuit includes a performance monitoring circuit which includes an adaptive adder circuit coupled to receive a first input signal indicative of a performance parameter of the integrated circuit and to provide a count value as a measure of the probability of the performance parameter. The adaptive adder circuit includes a random number generator circuit providing a random number, a counter circuit providing a count value and a comparator circuit coupled to compare the random number and the count value and to output a compare signal indicative thereof, the compare signal being provided to the counter as an up/down count signal. The adaptive adder circuit also includes a first logic circuit coupled to receive the performance parameter being measured and the compare signal which outputs a first signal which is used for controlling operation of the counter circuit.

Abstract: A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The operation of the communication port as a trace port and as a parallel debug port is mutually exclusive. The parallel debug port provides for transmission of debug information between a debug host controller and the processor. The parallel debug port and the trace port physically share pins. Bus request and grant signals are provided between the parallel debug port and a debug host controller to ensure that collisions do not occur between use by the trace port and the debug host controller. A separate serial debug port is also provided which can be used to enable the parallel debug port.

Abstract: A processor has both a serial debug port and a parallel debug port. The processor includes a processor core. The serial debug port is formed of a plurality of pins configured to send and receive signals to and from external software debug equipment. The parallel debug port is formed of a plurality of pins and configured to send and receive signals from external software debug equipment. A plurality of debug registers are accessible to the serial debug port and the parallel debug port. The debug registers are also coupled to the processor core for receiving and providing debug data and control signals. The processor core performs various software debug operations in response to signals from the external software debug equipment sent over one of the parallel and serial debug ports and communicates the results of the debug operation back over one of the serial and parallel debug ports.

Abstract: A processor provides trace synchronization information to ensure that address information for reconstructing instruction execution flow is provided in trace records with sufficient frequency. A trace record is provided for instructions that change the program flow such as conditional branches. However, target address information is not provided in the trace record for such instructions as conditional branches, only an indication of whether the branch was taken. Target address information is provided, however, for those instructions in which the target address is in some way data dependent. The processor determines whether each trace record includes address information. Each trace entry providing address information causes a counter to be reloaded to a predetermined value which is the desired maximum number of trace records generated before current program address information is provided. The counter counts each trace record produced which does not include address information.

Abstract: A system for handling multiple nested interrupts in a microprocessor device using C language interrupt handlers in which each interrupt handier is executed in two distinct stages, which are a Freeze mode handler and a signal handler, is disclosed. Upon the occurrence of each interrupt, a microprocessor of the device is placed in Freeze mode and the appropriate Freeze mode handler responds immediately to the interrupt, capturing all critical data and deactivating the interrupt request. Once the Freeze mode handler has completed execution, if execution of the signal handler is not necessary, an "interrupt return" or "IRET" instruction is executed, causing execution to return to the point at which the interrupt occurred. Otherwise, a signal number of the appropriate signal handler is pushed onto a signal stack stored in a memory associated with the microprocessor and a determination is made as to whether the signal dispatcher is running.

Abstract: An archery target comprising a stack of carpet strips placed upon a base, with the side edges of the strips facing toward the archer. The strips are maintained under compressive force by a pair of flexible bands wrapped around front and rear portions of the stack and the base. The stack preferably includes alternating strips of light weight commercial grade, medium weight plush, and heavy weight plush carpet, which can be waste strips from carpet manufacture or installation. The compressive force is adjusted to permit arrows shot at the target to penetrate at least six inches, but not more than ten inches. The target includes caster wheels attached to the base for rolling the target from one location to another. The target is extremely durable even if it is left exposed to adverse weather conditions. A smaller, portable version of the target is also disclosed. The target presents a minimal hazard to wayward arrows, thereby minimizing damage to arrows.