Patents by Inventor Daniel Mark Nelson
Daniel Mark Nelson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9959926Abstract: Write assist circuitry is disclosed to assist a memory device in changing logical states during a write operation. The write assist circuit includes write assist circuits which can be coupled to a shared boost capacitor to provide write assistance to the memory device. The write assist circuit includes boost switch circuit to selectively couple one or more of the write assist circuits and the shared boost capacitor. The one or more write assist circuits, when coupled to the shared capacitor, provide negative bitline assistance by selectively driving one of its corresponding bitlines pairs to be negative during a write operation.Type: GrantFiled: October 21, 2015Date of Patent: May 1, 2018Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Travis R. Hebig, Daniel Mark Nelson, Richard J. Stephani
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Publication number: 20170117034Abstract: Write assist circuitry is disclosed to assist a memory device in changing logical states during a write operation. The write assist circuit includes write assist circuits which can be coupled to a shared boost capacitor to provide write assistance to the memory device. The write assist circuit includes boost switch circuit to selectively couple one or more of the write assist circuits and the shared boost capacitor. The one or more write assist circuits, when coupled to the shared capacitor, provide negative bitline assistance by selectively driving one of its corresponding bitlines pairs to be negative during a write operation.Type: ApplicationFiled: October 21, 2015Publication date: April 27, 2017Applicant: Broadcom CorporationInventors: Travis R. HEBIG, Daniel Mark NELSON, Richard J. STEPHANI
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Patent number: 8860141Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.Type: GrantFiled: January 6, 2012Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Michael Launsbach, Daniel Mark Nelson
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Patent number: 8467230Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.Type: GrantFiled: October 6, 2010Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Michael Launsbach, Daniel Mark Nelson
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Patent number: 8159260Abstract: A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.Type: GrantFiled: October 5, 2010Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Daniel Mark Nelson
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Publication number: 20120087176Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.Type: ApplicationFiled: October 6, 2010Publication date: April 12, 2012Applicant: International Business Machines CorporationInventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Michael Launsbach, Daniel Mark Nelson
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Publication number: 20120081143Abstract: A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Daniel Mark Nelson
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Patent number: 7924633Abstract: A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.Type: GrantFiled: February 20, 2009Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Daniel Mark Nelson
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Patent number: 7911827Abstract: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.Type: GrantFiled: January 27, 2009Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
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Patent number: 7788554Abstract: A design structure embodied in a machine readable medium for implementing static random access memory (SRAM) cell write performance evaluation is provided. A SRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.Type: GrantFiled: October 16, 2007Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson
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Publication number: 20100214859Abstract: A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.Type: ApplicationFiled: February 20, 2009Publication date: August 26, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Daniel Mark Nelson
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Patent number: 7768851Abstract: A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.Type: GrantFiled: January 12, 2009Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson
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Publication number: 20100188886Abstract: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.Type: ApplicationFiled: January 27, 2009Publication date: July 29, 2010Applicant: International Business Machines CorporationInventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
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Patent number: 7751266Abstract: A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.Type: GrantFiled: June 26, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Derick Gardner Behrends, Daniel Mark Nelson, Jeffrey Milton Scherer
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Patent number: 7737757Abstract: Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.Type: GrantFiled: July 23, 2008Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
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Patent number: 7724586Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.Type: GrantFiled: August 20, 2008Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Todd Alan Christensen, Peter Thomas Freiburger, Daniel Mark Nelson
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Patent number: 7724585Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.Type: GrantFiled: August 20, 2008Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
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Publication number: 20100046277Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.Type: ApplicationFiled: August 20, 2008Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
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Publication number: 20100046278Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.Type: ApplicationFiled: August 20, 2008Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Allen Adams, Todd Alan Christensen, Peter Thomas Freiburger, Daniel Mark Nelson
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Publication number: 20100019824Abstract: Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.Type: ApplicationFiled: July 23, 2008Publication date: January 28, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith