Abstract: A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, a portion (42a) of the memory is connected directly to one of the requestors, such, as a host processor (10), so that high bandwidth transfers can be performed. A portion (42b) that is not selected to be in HOM mode can be accessed by other requestors or shut down to save power. The size (S1) of the portion of memory selected for HOM mode is selected to match the requirements of a given application and can be changed by writing a size value to a register.

Abstract: A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source port (460-461), a channel controller (410-412) and a destination port (460, 461). Channel to port buses (CP0-CP2) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC0-PC1) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry (420, 421) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller (460, 461) on each clock cycle for providing an address for a transaction performed on each clock cycle.

Abstract: A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, the memory is connected directly to one of the requestors, such as a host processor (10), so that high bandwidth transfers can be performed. The HOM access mode is entered when a priority assigned to the host processor is set to be higher than a priority assigned to any other requester. Registers for holding the priority assignments can be written by at least one of the requesters.

Abstract: A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source port (460-461), a channel controller (410-412) and a destination port (460, 461). Channel to port buses (CP0-CP2) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC0-PC1) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry (420, 421) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller (460, 461) on each clock cycle for providing an address for a transaction performed on each clock cycle.