Abstract: In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later time; (3) notifying second logic of the controller of the request; (4) determining at least one of whether the request is valid and enough buffers are available to complete the request; (5) programming a filtering pipe; and (6) responding to the first logic based on at least one of whether the request is valid and enough buffers are available to complete the request such that the first logic may employ the filtering pipe to complete the request. The first logic operates in a first clock domain and second logic operates in a second clock domain. Numerous other aspects are provided.

Abstract: A standalone hardware engine is used on an advanced function storage adaptor to improve the performance of a Reed-Solomon-based RAID-6 implementation. The engine can perform the following operations; generate P and Q parity for a full stripe write, generate updated P and Q parity for a partial stripe write, generate updated P and Q parity for a single write to one drive in a stripe, generate the missing data for one or two drives. The engine requires all the source data to be in the advanced function storage adaptor memory (external DRAM) before it is started, the engine only needs to be invoked once to complete any of the four above listed operations, the engine will read the source data only once and output to memory the full results for any of the listed four operations. In some prior-art systems, for N inputs, there would be 6N+2 memory accesses. With this approach, the same operation would require only N+2 memory accesses.

Abstract: A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.

Abstract: In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later time; (3) notifying second logic of the controller of the request; (4) determining at least one of whether the request is valid and enough buffers are available to complete the request; (5) programming a filtering pipe; and (6) responding to the first logic based on at least one of whether the request is valid and enough buffers are available to complete the request such that the first logic may employ the filtering pipe to complete the request. The first logic operates in a first clock domain and second logic operates in a second clock domain. Numerous other aspects are provided.

Abstract: A flow through asynchronous elastic first-in, first-out (FIFO) apparatus and method are provided for implementing multi-engine parsing and authentication. A FIFO random access memory (RAM) has a data input for receiving data and control information and a data output for outputting the data and control information. The FIFO RAM includes a plurality of locations for storing a plurality of words, each word including a set number of bits. Write clocked logic is provided for loading the data and control information to the FIFO RAM at a first clock frequency. Asynchronous read clocked logic is provided for outputting the data and control information from the FIFO RAM at a second clock frequency. The first clock frequency of the write clocked logic and the second clock frequency of the asynchronous read clocked logic and a data width of the FIFO RAM are selectively provided for outputting the data and control information from the FIFO RAM with no back pressure.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment determine whether a current number of buffers allocated to a queue pair is less than a maximum number of buffers for the queue pair, decide whether a current number of buffers allocated to an operation type is less than a maximum number of buffers for the operation, and allocate a buffer to the queue pair if the queue pair requests the buffer for an operation having the operation type and the determining and the deciding are true. In this way, too much buffer space is prevented from being assigned to particular operation and to a particular queue pair.