Patents by Inventor Daniel Namishia
Daniel Namishia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162304Abstract: A transistor device may include a semiconductor structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer; a source contact and a drain contact on the barrier layer; a gate contact on the semiconductor structure between the source contact and the drain contact, the gate contact including a drain-side wing portion extending from a central portion of the gate contact; and a field plate on the semiconductor structure between the gate contact and the drain contact and laterally offset from the gate contact by a distance. The field plate may include a first wing portion extending from a central portion of the field plate.Type: ApplicationFiled: January 9, 2024Publication date: May 16, 2024Inventors: Jeremy Fisher, Kyle Bothe, Terry Alcorn, Daniel Namishia, Jia Guo, Matthew King, Saptharishi Sriram, Fabian Radulescu, Scott Sheppard, Yueying Liu
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Publication number: 20240106397Abstract: A transistor amplifier package includes a package substrate comprising conductive patterns exposed by solder mask patterns at a surface thereof, and at least one transistor die comprising a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask patterns such that respective gate, drain, and/or source terminals of the at least one transistor die are electrically connected to respective ones of the conductive patterns. Related transistor amplifiers and fabrication methods are also discussed.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Marvin Marbell, Jeremy Fisher, Haedong Jang, Daniel Namishia, Daniel Etter
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Patent number: 11842937Abstract: A transistor device includes a substrate, a semiconductor structure on the substrate, a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulant surface that is opposite the non-planar surface, and a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface.Type: GrantFiled: July 30, 2021Date of Patent: December 12, 2023Assignee: Wolfspeed, Inc.Inventors: Chris Hardiman, Daniel Namishia, Kyle Bothe, Elizabeth Keenan
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Patent number: 11842997Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.Type: GrantFiled: March 21, 2022Date of Patent: December 12, 2023Assignee: Wolfspeed, Inc.Inventors: Terry Alcorn, Daniel Namishia, Fabian Radulescu
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Patent number: 11769768Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.Type: GrantFiled: June 1, 2020Date of Patent: September 26, 2023Assignee: Wolfspeed, Inc.Inventors: Terry Alcorn, Daniel Namishia, Fabian Radulescu
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Patent number: 11646310Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.Type: GrantFiled: June 1, 2020Date of Patent: May 9, 2023Assignee: Wolfspeed, Inc.Inventors: Terry Alcorn, Daniel Namishia, Fabian Radulescu
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Patent number: 11587842Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: October 29, 2020Date of Patent: February 21, 2023Assignee: Wolfspeed, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Publication number: 20230029763Abstract: A semiconductor die includes a semiconductor body having a gate, a source contact, and a drain contact thereon, a metal contact structure on the semiconductor body and electrically connected to the gate, the source contact, or the drain contact, and an encapsulation structure. The encapsulation structure includes first and second encapsulation layers of respective non-conductive materials stacked on the metal contact structure, and an opening extending therethrough to expose the metal contact structure. The opening includes a sidewall having a substantially continuous slope that extends through the first and second encapsulation layers to the metal contact structure. Related devices and fabrication methods are also discussed.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Christopher Hardiman, Daniel Namishia, Kyle Bothe, Elizabeth Keenan, David Santa Ana, Daniel Etter
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Publication number: 20230031205Abstract: A transistor device includes a substrate, a semiconductor structure on the substrate, a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulant surface that is opposite the non-planar surface, and a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Chris Hardiman, Daniel Namishia, Kyle Bothe, Elizabeth Keenan
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Publication number: 20220384290Abstract: A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sublayers that are stacked on the semiconductor body. Each of the sublayers comprises a respective stress in one or more directions, where the respective stresses of at least two of the sublayers are different. The sublayers may include a first stressor sublayer comprising first stress, and a second stressor sublayer comprising a second stress that at least partially compensates for the first stress in the one or more directions. Related devices and methods of fabrication are also discussed.Type: ApplicationFiled: February 3, 2022Publication date: December 1, 2022Inventors: Kyoung-Keun Lee, Daniel Etter, Fabian Radulescu, Scott Sheppard, Daniel Namishia
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Publication number: 20220384366Abstract: A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes first and second sublayers of first and second oxide materials, respectively, where the first oxide material is different than the second oxide material. Related devices and fabrication methods are also discussed.Type: ApplicationFiled: June 1, 2021Publication date: December 1, 2022Inventors: Kyoung-Keun Lee, Fabian Radulescu, Scott Sheppard, Daniel Namishia
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Publication number: 20220208758Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.Type: ApplicationFiled: March 21, 2022Publication date: June 30, 2022Inventors: Terry Alcorn, Daniel Namishia, Fabian Radulescu
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Publication number: 20210375856Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.Type: ApplicationFiled: June 1, 2020Publication date: December 2, 2021Inventors: Terry Alcorn, Daniel Namishia, Fabian Radulescu
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Publication number: 20210043530Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: October 29, 2020Publication date: February 11, 2021Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Patent number: 10886189Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: May 1, 2019Date of Patent: January 5, 2021Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Patent number: 10840162Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: May 1, 2019Date of Patent: November 17, 2020Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Publication number: 20190259682Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Patent number: 10332817Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: December 1, 2017Date of Patent: June 25, 2019Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Publication number: 20190172769Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: December 1, 2017Publication date: June 6, 2019Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Patent number: 10068834Abstract: Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.Type: GrantFiled: March 4, 2013Date of Patent: September 4, 2018Assignee: Cree, Inc.Inventors: Sarah Kay Haney, Brett Hull, Daniel Namishia