Patents by Inventor Daniel Ng
Daniel Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961225Abstract: One or more machine learning techniques can be used to identify locations of potential malignancies within images (e.g., video images) captured during a medical procedure, such as an endoscopic procedure. The images can be displayed, in real-time, on a display unit. The images can be displayed with a graphical overlay that isolates the identified locations of potential malignancies.Type: GrantFiled: July 21, 2020Date of Patent: April 16, 2024Assignee: Iterative Scopes, Inc.Inventors: Jonathan Ng, Sloane Allebes Phillips, Amit Ranade, Daniel Wang, Perikumar Mukundbhai Javia, Avi Walden, Austin Wang, Evan Wlodkowski, Samriddhi Dhakal
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Publication number: 20240109071Abstract: A method of thermal cycling a droplet, including providing a droplet actuator with heaters establishing a first thermal zone and second thermal zone in a substantially oil-filled droplet operations gap; a thermal cycling path comprising droplet operations electrodes comprising a first droplet operations electrode in the first thermal zone and a second droplet operations electrode in the second thermal zone, wherein the first and second droplet operations electrodes are within 5 mm of each other; a first temperature at the first droplet operations electrode and a second temperature at the second droplet operations electrode, wherein the first and second temperatures differ by at least about 10° C.; and using the droplet operations electrodes, transporting the droplet in a cycling pattern for multiple cycles along the thermal cycling path between the first droplet operations electrode and the second droplet operations electrode. Cartridges and systems are also provided.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Applicant: Baebies, Inc.Inventors: Daniel Wu, Rainer Ng, Greg Smith, Vijay Srinivasan, Vamsee Pamula
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Patent number: 11918582Abstract: Disclosed herein are pyrazole pyrimidine compounds that modulate and/or inhibit hematopoietic progenitor kinase 1, as well as methods of making such compounds and therapeutic methods of using same.Type: GrantFiled: March 14, 2022Date of Patent: March 5, 2024Assignee: RAPT Therapeutics, Inc.Inventors: Cyril Bucher, Adrian Dukes, Blanca Gomez, Hannah Haley, Dennis Hu, Jeffrey J. Jackson, Michelle Yoo Min Ko, Paul Leger, Anqi Ma, Andrew A. Ng, Daniel Poon, Omar Robles, Anton Shakhmin, Grant Shibuya, Parcharee Tivitmahaisoon, Vi-Anh Vu, David J. Wustrow, Mikhail Zibinsky
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Patent number: 11307917Abstract: The disclosure relates to a decentralized cyber-physical system including a managing unit and a plurality of components. The managing unit includes a root resilient manager including a root contract and a sub-contract generator. The sub-contract generator is configured to decompose the root contract into a plurality of sub-contracts and assign the plurality of sub-contracts to the plurality of components, respectively. Each component includes at least one observer configured to monitor if the property of the individual component violates the sub-contracts corresponding thereto. When one of the plurality of sub-contracts violates during the runtime of the decentralized cyber-physical system, the root resilience manager issues an alarm.Type: GrantFiled: August 13, 2020Date of Patent: April 19, 2022Assignee: DELTA ELECTRONICS INTL (SINGAPORE) PTE LTDInventors: Zhiheng Xu, Jun Xian Daniel Ng, Omar Bataineh, Arvind Easwaran, Sidharta Andalam, Bo Woon Jeffrey Soon
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Publication number: 20210049061Abstract: The disclosure relates to a decentralized cyber-physical system including a managing unit and a plurality of components. The managing unit includes a root resilient manager including a root contract and a sub-contract generator. The sub-contract generator is configured to decompose the root contract into a plurality of sub-contracts and assign the plurality of sub-contracts to the plurality of components, respectively. Each component includes at least one observer configured to monitor if the property of the individual component violates the sub-contracts corresponding thereto. When one of the plurality of sub-contracts violates during the runtime of the decentralized cyber-physical system, the root resilience manager issues an alarm.Type: ApplicationFiled: August 13, 2020Publication date: February 18, 2021Inventors: Zhiheng Xu, Jun Xian Daniel Ng, Omar Bataineh, Arvind Easwaran, Sidharta Andalam, Bo Woon Jeffrey Soon
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Patent number: 10686035Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: GrantFiled: October 9, 2018Date of Patent: June 16, 2020Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Patent number: 10608092Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.Type: GrantFiled: December 16, 2017Date of Patent: March 31, 2020Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
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Publication number: 20190115427Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: October 9, 2018Publication date: April 18, 2019Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Patent number: 10192982Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.Type: GrantFiled: August 18, 2017Date of Patent: January 29, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
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Patent number: 10121857Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: GrantFiled: May 1, 2015Date of Patent: November 6, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Publication number: 20180269293Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.Type: ApplicationFiled: December 16, 2017Publication date: September 20, 2018Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
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Publication number: 20180240872Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: May 1, 2015Publication date: August 23, 2018Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Patent number: 10014381Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.Type: GrantFiled: January 5, 2016Date of Patent: July 3, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
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Patent number: 9960237Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.Type: GrantFiled: April 13, 2015Date of Patent: May 1, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
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Patent number: 9876096Abstract: A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate . A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 ?m to 0.2 ?m.Type: GrantFiled: October 27, 2016Date of Patent: January 23, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Madhur Bobde, Sik Lui, Hamza Yilmaz, Jongoh Kim, Daniel Ng
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Publication number: 20170373185Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.Type: ApplicationFiled: August 18, 2017Publication date: December 28, 2017Inventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
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Patent number: 9806175Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.Type: GrantFiled: February 23, 2015Date of Patent: October 31, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Daniel Ng., Tiesheng Li, Sik K. Lui
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Patent number: 9748375Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.Type: GrantFiled: March 4, 2016Date of Patent: August 29, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
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Patent number: 9620498Abstract: A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.Type: GrantFiled: July 26, 2014Date of Patent: April 11, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yi Su, Anup Bhalla, Daniel Ng
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Publication number: 20170053989Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.Type: ApplicationFiled: April 13, 2015Publication date: February 23, 2017Inventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng