Abstract: An error correction code (ECC) generator/checker for processing high bandwidth data block transfers. The high bandwidth ECC generator/checker logic includes a plurality stages, each stage including Reed-Solomon Cyclic Redundancy Check (RS CRC) code logic for processing a single data word. The stages can be configured to operate in parallel to process multiple-word parallel, high bandwidth transfers, or individually wherein each stage processes data in a word-serial manner. Each stage includes a first input for receiving a respective word portion of a multiple-word transfer, a second input for receiving either an intermediate ECC value from a previous stage or a feed back value, means for combining data words received at the first and second inputs, an alpha multiplier and an output for providing an ECC word.