Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Abstract: A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.

Abstract: A semiconductor wafer includes: a first main surface and a second main surface opposite the first main surface; a detachment plane parallel to the first main surface inside the semiconductor wafer, the detachment plane defined by defects; electronic semiconductor components formed at the first main surface and between the first main surface and the detachment plane; and a glass structure attached to the first main surface. The glass structure includes openings, each of which leaves a respective area of the electronic semiconductor components uncovered. A method of processing the wafer, a clip, and a semiconductor device are also described.

Abstract: A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.

Abstract: A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.

Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Abstract: A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.

Abstract: A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.

Abstract: A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including Ni3Sn4.

Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

Abstract: An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract: A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.

Abstract: An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.