Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: An input buffer generates an output signal corresponding to a digital input signal. The input buffer is coupled to a feedback circuit. The feedback circuit initially couples a positive feedback signal to the buffer circuit responsive to each transition of the input signal. The positive feedback signal increases the gain of the input buffer thereby causing the input buffer to transition the output signal more quickly in response to the transition of the input signal. The feedback circuit thereafter terminates the positive feedback signal before a subsequent transition of the input signal. The positive feedback signal is generated by detecting a transition of the output signal responsive to the transition of the input signal that initiated the positive feedback signal.

Abstract: A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.

Abstract: A differential receiver circuit on an integrated circuit consumes substantially no standby power, has constant propagation delay regardless of the input common mode bias, has acceptable common mode rejection and includes first and second pass circuits and buffers to receive differential input signals. The first pass circuit provides a true output signal based on a differential between the “true” buffered signal and the complimentary buffered signal. The second pass circuit provides a “complementary” output signal based on a differential between the complimentary buffered signal and the “true” buffered signal. The differential receiver circuit rejects common mode biases that may be present on the received differential signals without varying propagation delay times.

Abstract: A voice-controlled martial arts exercise device is comprised of targets for the user to strike with hands, feet, elbows, or knees. A processor system is interfaced to recognize voice commands from the user and to detect when a target has been hit and also controls a pixelized visual display and audio system. These elements are used to provide an entertaining and challenging assortment of games and drills with which the user can interact by voice commands as well as by striking the targets. Additionally, motorized limbs are optionally included which can strike at the user under processor or manual control; the user must block or avoid these strikers. The method of using voice command recognition and a pixelized visual display controlled by a processor system provides unique advantages, including much more abstract and complicated interaction than is otherwise possible for a martial arts exercise system, which allows for much more entertaining and sustained use.

Abstract: A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.