Abstract: In operation, a standard cell library having diode place-holders (16) associated with standard cell inputs (12) is used to design a standard cell-based semiconductor device. Each standard cell in the standard cell-based semiconductor device is analyzed to determine if its standard cell inputs (12) will be connected to a conductive element (18) during processing that can accumulate a charge. When a conductive element (18) that can accumulate charge is identified, the diode place-holder (16) associated with its standard cell input (12) is replaced with a diode (16).

Abstract: In operation, a standard cell library having diode place-holders (16) associated with standard cell inputs (12) is used to design a standard cell-based semiconductor device. Each standard cell in the standard cell-based semiconductor device is analyzed to determine if its standard cell inputs (12) will be connected to a conductive element (18) during processing that can accumulate a charge. When a conductive element (18) that can accumulate charge is identified, the diode place-holder (16) associated with its standard cell input (12) is replaced with a diode (16).

Abstract: A peripheral controller interconnect/industry standard architecture (PCI/ISA)bridge is coupled between the PCI and ISA buses in a computer system. A PCI master in the system asserts address and address parity information on the PCI bus to initiate a master-slave transaction over the PCI bus. The bridge includes logic for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge also includes a PCI slave that receives the address parity error signal and generates a target-abort signal in response if the PCI slave has already claimed the address by asserting a device select signal. The bridge also includes logic that prevents the target-abort signal from propagating to the PCI bus whenever this logic receives both the address parity error signal and the device select signal.

Abstract: A data processing system (10) for providing memory access to a memory (18). The memory (18) includes a memory array (43) having a plurality of memory cells arranged in rows and columns and an address decoder (42) for accessing a memory cell (44) of the memory array (43) in response to decoding an address signal. Precharge logic (49) coupled to the memory array (43) and the address decoder (42) enables, in a high performance mode, all columns of the memory array (43) prior to accessing the memory cell (44). In a low power mode, the precharge logic (49) enables only selected columns of the memory array (43) prior to accessing the memory cell (44).

Abstract: A computer system having an ISA bus and a PCI bus is provided with a PCI to ISA bridge having certain imbedded functions performed by PCI slaves on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

Abstract: A system having an industry standard architecture (ISA) bus with a 24-bit memory addressing capacity and a peripheral controller interconnect (PCI) bus with a 32-bit memory addressing capacity, is provided with a bridge coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) controller circuit that generates 32-bit memory addresses for DMA transfer operations over the PCI bus. The DMA controller circuit includes a pair of cascaded DMA controllers that generate the 16 least significant bits of the 32-bit memory addresses, and address extension logic having a low page register that provides the 8 next most significant bits of the 32-bit memory addresses, and a high page register that provides the 8 most significant bits of the 32-bit memory addresses. The 16 bits provided by the low and high page registers are concatenated with the lower 16 bits to form the 32-bit addresses.

Abstract: A bridge interface for buses in a computer system has a direct memory access (DMA) controller that controls memory transfers in the computer system. The DMA controller has a pair of cascaded DMA controller chips that provide a plurality of DMA channels. A multiplexer circuit receives memory address signals from the DMA controller chips. The memory address signals are received in both a shifted form and an unshifted form at the multiplexer inputs. By selection of the shifted or the unshifted memory address at the multiplexer, either even or odd addresses are produced at the multiplexer output for each DMA channel, thereby selectively providing 8-bit or 16-bit memory accesses. The control of the multiplexer is programmable for each DMA channel, providing dynamic configuration of the DHA channels as either 8-bit or 16-bit channels.

Abstract: A bridge interface for a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer, and a scatter/gather unit coupled between the ISA bus and the DMA control circuit. The scatter/gather unit selectively provides the programming signals to the DMA control circuit directly or causes the programming signals to be provided over the ISA bus. Providing the programming signals to the DMA control circuit directly from the programming controller of the scatter/gather unit takes advantage of the location of both the DMA control circuit and the scatter/gather unit on the bridge chip.