Patents by Inventor Daniel R. Cutter

Daniel R. Cutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cryptographic system, method and multiplier
    Patent number: 8073892
    Abstract: In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 6, 2011
    Assignee: Intel Corporation
    Inventors: Wajdi K. Feghali, William C. Hasenplaugh, Gilbert M. Wolrich, Daniel R. Cutter, Vinodh Gopal, Gunnar Gaubatz
  • CRYPTOGRAPHIC SYSTEM, METHOD AND MULTIPLIER
    Publication number: 20110264720
    Abstract: In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
    Type: Application
    Filed: December 30, 2005
    Publication date: October 27, 2011
    Inventors: Wajdi Feghali, William C. Hasenplaugh, Gilbert M. Wolrich, Daniel R. Cutter, Vinodh Gopal, Gunnar Gaubatz
  • System and method for cryptography processing units and multiplier
    Patent number: 7725624
    Abstract: In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Wajdi K. Feghali, William C. Hasenplaugh, Gilbert M. Wolrich, Daniel R. Cutter, Vinodh Gopal, Gunnar Gaubatz