Abstract: Embodiments herein relate to systems, apparatuses, or techniques for using an optical physical layer die within a system-on-a-chip to optically couple with an optical physical layer die on another package to provide high-bandwidth memory access between the system-on-a-chip and the other package. In embodiments, the other package may be a large optically connected memory device that includes a memory controller coupled with an optical physical layer die, where the memory controller is coupled with memory. Other embodiments may be described and/or claimed.

Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.

Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.

Abstract: In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.

Abstract: An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.