Patents by Inventor Daniel T. Pham
Daniel T. Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12004410Abstract: An optical system includes a light source, an optical film curved about a first axis, and a light control film curved about the first axis and disposed between the light source and the optical film. The optical film includes a microstructured first major surface and an opposing second major surface. The microstructured first major surface defines a linear Fresnel lens including a plurality of Fresnel elements extending longitudinally along the first axis. The first major surface of the optical film faces the light control film. The light control film includes a plurality of alternating optically transmissive and optically absorptive regions extending longitudinally along the first axis such that in a cross-section orthogonal to the first axis, for at least a majority of the optically transmissive regions, a centerline between adjacent optically absorptive regions is substantially normal to a major surface of the light control film.Type: GrantFiled: October 29, 2020Date of Patent: June 4, 2024Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Tao Liu, Gary T. Boyd, Daniel J. Schmidt, Caleb T. Nelson, Owen M. Anderson, Tri D. Pham, Encai Hao, Shu-Ching Fan
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Publication number: 20240168204Abstract: An optical construction includes a lens film having a plurality of optically transparent first beads at least partially embedded in a first layer. A light blocking second layer is disposed on the lens film and defines a plurality of through openings therein extending at least partially between opposite major top and bottom surfaces of the second layer. The through openings are aligned to the first beads in a one-to-one correspondence.Type: ApplicationFiled: March 10, 2022Publication date: May 23, 2024Inventors: Bert T. Chien, William B. Kolb, Tri D. Pham, Daoyun Song, Daniel K. Bruesewitz, Stephen P. Maki, James A. Phipps, Jonah Shaver, Zhaohui Yang
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Publication number: 20240151880Abstract: An optical film includes a structured film and a light control film formed on the structured film. The structured film includes a substrate and a plurality of polymeric microstructures formed on a major surface of the substrate. Each microstructure includes an optical facet and a sidewall meeting the optical facet at a ridge of the microstructure. The light control film includes an optically transparent material disposed on and covering the plurality of polymeric microstructures, and a plurality of optically absorptive louvers formed in the optically transparent material opposite the structured film. The louvers extend along a longitudinal direction and are spaced apart along an orthogonal transverse direction. The louvers have an average depth D into the optically transparent material and have an average width W in the transverse direction. D/W can be greater than 2. The optical film is integrally formed.Type: ApplicationFiled: November 4, 2020Publication date: May 9, 2024Inventors: Tao Liu, Tri D. Pham, Gary T. Boyd, Daniel J. Schmidt, Caleb T. Nelson, Owen M. Anderson
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Publication number: 20240142673Abstract: An optical film has a major surface including a plurality of microstructures. Each microstructure includes an optical facet and a sidewall meeting the optical facet at a ridge of the microstructure. The optical facet and the sidewall define an oblique angle therebetween. For each microstructure in at least a majority of the microstructures, an optically absorptive layer is disposed on the sidewall. The optical film can include a polymeric layer having a microstructured surface at least partially coated with an inorganic optically transparent layer. The optically absorptive layer can an average thickness t where 100 nm<t<1 micrometer. A first layer can be disposed between the sidewall and the optically absorptive layer where the first layer has a lower extinction coefficient than the optically absorptive layer.Type: ApplicationFiled: October 29, 2020Publication date: May 2, 2024Inventors: Tao Liu, Gary T. Boyd, Daniel J. Schmidt, Caleb T. Nelson, Owen M. Anderson, Tri D. Pham
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Publication number: 20240122043Abstract: An optical system includes a light source, an optical film curved about a first axis, and a light control film curved about the first axis and disposed between the light source and the optical film. The optical film includes a microstructured first major surface and an opposing second major surface. The microstructured first major surface defines a linear Fresnel lens including a plurality of Fresnel elements extending longitudinally along the first axis. The first major surface of the optical film faces of the optically transmissive regions, a centerline between adjacent optically absorptive regions is substantially normal to a major surface of the light control film.Type: ApplicationFiled: October 29, 2020Publication date: April 11, 2024Inventors: Tao Liu, Gary T. Boyd, Daniel J. Schmidt, Caleb T. Nelson, Owen M. Anderson, Tri D. Pham, Encai Hao, Shu-Ching Fan
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Publication number: 20240092054Abstract: A thermoplastic film which exhibits elastic-like behavior along at least one axis when stretched or elongated and then released. The thermoplastic film comprises a plurality of raised rib-like elements extending in a direction perpendicular to a main surface of the thermoplastic film. The thermoplastic film further includes a plurality of web areas positioned about the plurality of raised rib-like elements. The plurality of raised rib-like elements and plurality of web areas are arranged in a complex pattern. The complex pattern provides visual and tactile cues as the films are stretched or elongated. The complex pattern can cause the thermoplastic film to have a complex stretch profile.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Shaun T. Broering, Michael G. Borchardt, Ranyi Zhu, Jason R. Maxwell, Daniel Charles Peck, Hugh Joseph O’Donnell, Robert T. Dorsey, Lehai Minh Pham Vu, Karen Denise McAffry
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Patent number: 9466491Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.Type: GrantFiled: May 2, 2014Date of Patent: October 11, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel T. Pham, Hyun-Jin Cho, Ruilong Xie
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Patent number: 9263585Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.Type: GrantFiled: October 30, 2012Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel T. Pham, Robert J. Miller, Kungsuk Maitra
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Patent number: 9184263Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.Type: GrantFiled: December 30, 2013Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Xiuyu Cai, Ajey Poovannummoottil Jacob, Daniel T. Pham, Mark V. Raymond, Christopher M. Prindle, Catherine B. Labelle, Linus Jang, Robert Teagle
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Publication number: 20150318178Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.Type: ApplicationFiled: May 2, 2014Publication date: November 5, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Daniel T. Pham, Hyun-Jin Cho, Ruilong Xie
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Publication number: 20150187905Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.Type: ApplicationFiled: December 30, 2013Publication date: July 2, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Xiuyu Cai, Ajey Poovannummoottil Jacob, Daniel T. Pham, Mark V. Raymond, Christopher M. Prindle, Catherine B. Labelle, Linus Jang, Robert Teagle
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Patent number: 9064932Abstract: One method disclosed includes, among other things, forming an uncut line-type gate structure above first and second spaced-apart active regions of a semiconductor substrate, forming a sidewall spacer around a perimeter of the line-type gate structure, performing at least one etching process to remove an axial portion of a gate cap layer and an axial portion of a gate electrode that are positioned above the isolation region so as to thereby define first and second cut end surfaces of first and second gate electrodes, respectively, and an isolation plug cavity and forming a gate cut isolation plug in the isolation plug cavity.Type: GrantFiled: May 2, 2014Date of Patent: June 23, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel T. Pham, Zhenyu Hu
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Patent number: 8877588Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.Type: GrantFiled: February 11, 2013Date of Patent: November 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel T. Pham, Werner Juengling, William J. Taylor, Jr., Robert Miller
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Patent number: 8853019Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.Type: GrantFiled: March 13, 2013Date of Patent: October 7, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Jody A. Fronheiser, Jeremy A. Wahl, Kerem Akarvardar, Ajey P. Jacob, Daniel T. Pham
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Publication number: 20140273423Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Jody A. Fronheiser, Jeremy A. Wahl, Kerem Akarvardar, Ajey P. Jacob, Daniel T. Pham
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Publication number: 20140225168Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.Type: ApplicationFiled: February 11, 2013Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Daniel T. Pham, Werner Juengling, William J. Taylor, JR., Robert Miller
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Patent number: 8728885Abstract: One method herein includes forming a plurality of spaced-apart trenches that extend at least partially into a semiconducting substrate, wherein the trenches define a fin structure comprised of first and second layers of semiconducting material, wherein the first layer of semiconducting material is selectively etchable relative to the substrate and the second layer of semiconducting material, forming a sacrificial gate structure above the fin, wherein the gate structure includes a gate insulation layer and a gate electrode, forming a sidewall spacer adjacent the gate structure, performing an etching process to remove the sacrificial gate structure, thereby defining a gate cavity, performing at least one selective etching process to selectively remove the first layer of semiconducting material relative to the second layer of semiconducting material within the gate cavity, thereby defining a space between the second semiconducting material and the substrate, and forming a final gate structure in the gate cavity.Type: GrantFiled: December 27, 2012Date of Patent: May 20, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel T. Pham, Jody Fronheiser, William J. Taylor, Jr.
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Publication number: 20140120677Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.Type: ApplicationFiled: October 30, 2012Publication date: May 1, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Daniel T. Pham, Robert J. Miller, Kungsuk Maitra
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Patent number: 8669147Abstract: Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.Type: GrantFiled: June 11, 2012Date of Patent: March 11, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel T. Pham, Robert J. Miller, Kingsuk Maitra
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Patent number: 8664093Abstract: Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.Type: GrantFiled: May 21, 2012Date of Patent: March 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel T. Pham, William J. Taylor, Jr.