Abstract: A semiconductor arrangement has a substrate which carries a partially filled array of semiconductor cells, and utilises the vacant sites in the array to position interconnecting tracks. A filled array is manufactured, and when the electrical function of the arrangement has been allocated, those semiconductor cells, each of which contains active semiconductor devices, which are not needed to perform the allocated function are removed. The vacant sites so formed are then occupied by electrically conductive tracks. The arrangement is suitable for silicon-on-sapphire gate arrays.

Abstract: A force sensor comprising a field effect transistor (FET) structure formed on a substrate, having an insulating layer overlying the substrate adjacent to the channel region of the transistor structure. A layer of piezoelectric material overlies the insulating layer, the layer of piezoelectric material having a portion which extends beyond the insulating layer to form a cantilever structure overhanging a portion of the channel region. A control electrode overlies the cantilever structure. Forces acting on the cantilever structure modify the charge distribution in the underlaying channel region, thereby to cause the drain current of the transistor to vary with any variation of force on the cantilever structure.