Patents by Inventor Daniel V. Rosa

Daniel V. Rosa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11366759
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: June 21, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum
  • Publication number: 20210096998
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.
    Type: Application
    Filed: December 10, 2020
    Publication date: April 1, 2021
    Inventors: Bruce C. GIAMEI, Christian JACOBI, Daniel V. ROSA, Anthony SAPORITO, Donald W. SCHMIDT, Chung-Lung K. SHUM
  • Patent number: 10956337
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum
  • Patent number: 10621090
    Abstract: A computing environment facility is provided to extend a hold of a cache line in private (or local) cache exclusively after processing a storage operand request. The facility includes determining whether a storage operand request to a storage location shared by multiple processing units of the computing environment is designated hold. In addition, a determination is made whether a state of the corresponding cache line in private cache used for processing the storage operand request is owned exclusively. Based on determining that the storage operand request is designated hold, and that the state of the corresponding cache line in private cache used for processing the storage operand request is owned exclusively, continuing to hold the corresponding cache line in the private cache exclusively after completing processing of the storage operand request. The continuing to hold may include initiating a counter to facilitate the continuing hold for a desired, set interval.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum
  • Patent number: 10534557
    Abstract: A system and method for implementing a servicing instruction for a plurality of counters that includes determining a counter set based on the servicing instruction, whether access is authorized to the counter set, and a block of storage in a memory based on the service instruction. In response to the determining that the access is authorized, the system and method extracts the plurality of counters within the counter set in response to the determining that the access is authorized and storing the plurality of counters in the block of storage.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Jonathan D. Bradbury, Daniel V. Rosa, Donald W. Schmidt
  • Patent number: 10521351
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: December 31, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum
  • Publication number: 20190391922
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.
    Type: Application
    Filed: September 5, 2019
    Publication date: December 26, 2019
    Inventors: Bruce C. GIAMEI, Christian JACOBI, Daniel V. ROSA, Anthony SAPORITO, Donald W. SCHMIDT, Chung-Lung K. SHUM
  • Patent number: 10303575
    Abstract: A facility is provided for collecting time-slice-instrumentation information during processing unit execution. The facility counts, at least in part, occurrence of a specified processing unit event during a time-slice of processing unit execution. The counted events occurring during a first interval of execution and a second interval of execution of the time-slice are retained. The first interval of execution is earlier in the time-slice than the second interval of execution, and the counted events facilitate adjusting performance of the processing unit. In an embodiment, the time-slice is a contiguous period of time of processing unit execution, and the specified processing unit event includes a cache event. The processing unit may interleave processing of multiple different units of work across multiple contiguous time-slices, and during a single time-slice, a single unit of work of the multiple different units of work is processed by the processing unit.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt
  • Patent number: 10102004
    Abstract: Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Jonathan D. Bradbury, Gary M. King, Daniel V. Rosa, Donald W. Schmidt
  • Patent number: 10095523
    Abstract: Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Jonathan D. Bradbury, Gary M. King, Daniel V. Rosa, Donald W. Schmidt
  • Publication number: 20180196751
    Abstract: A computing environment facility is provided to extend a hold of a cache line in private (or local) cache exclusively after processing a storage operand request. The facility includes determining whether a storage operand request to a storage location shared by multiple processing units of the computing environment is designated hold. In addition, a determination is made whether a state of the corresponding cache line in private cache used for processing the storage operand request is owned exclusively. Based on determining that the storage operand request is designated hold, and that the state of the corresponding cache line in private cache used for processing the storage operand request is owned exclusively, continuing to hold the corresponding cache line in the private cache exclusively after completing processing of the storage operand request. The continuing to hold may include initiating a counter to facilitate the continuing hold for a desired, set interval.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 12, 2018
    Inventors: Bruce C. GIAMEI, Christian JACOBI, Daniel V. ROSA, Anthony SAPORITO, Donald W. SCHMIDT, Chung-Lung K. SHUM
  • Publication number: 20180196754
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 12, 2018
    Inventors: Bruce C. GIAMEI, Christian JACOBI, Daniel V. ROSA, Anthony SAPORITO, Donald W. SCHMIDT, Chung-Lung K. SHUM
  • Publication number: 20180196727
    Abstract: A facility is provided for collecting time-slice-instrumentation information during processing unit execution. The facility counts, at least in part, occurrence of a specified processing unit event during a time-slice of processing unit execution. The counted events occurring during a first interval of execution and a second interval of execution of the time-slice are retained. The first interval of execution is earlier in the time-slice than the second interval of execution, and the counted events facilitate adjusting performance of the processing unit. In an embodiment, the time-slice is a contiguous period of time of processing unit execution, and the specified processing unit event includes a cache event. The processing unit may interleave processing of multiple different units of work across multiple contiguous time-slices, and during a single time-slice, a single unit of work of the multiple different units of work is processed by the processing unit.
    Type: Application
    Filed: January 10, 2017
    Publication date: July 12, 2018
    Inventors: Bruce C. GIAMEI, Christian JACOBI, Daniel V. ROSA, Anthony SAPORITO, Donald W. SCHMIDT
  • Publication number: 20170371549
    Abstract: A system and method for implementing a servicing instruction for a plurality of counters that includes determining a counter set based on the servicing instruction, whether access is authorized to the counter set, and a block of storage in a memory based on the service instruction. In response to the determining that the access is authorized, the system and method extracts the plurality of counters within the counter set in response to the determining that the access is authorized and storing the plurality of counters in the block of storage.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 28, 2017
    Inventors: Jane H. Bartik, Jonathan D. Bradbury, Daniel V. Rosa, Donald W. Schmidt
  • Patent number: 9760302
    Abstract: A system and method for implementing a servicing instruction for a plurality of counters that includes determining a counter set based on the servicing instruction, whether access is authorized to the counter set, and a block of storage in a memory based on the service instruction. In response to the determining that the access is authorized, the system and method extracts the plurality of counters within the counter set in response to the determining that the access is authorized and storing the plurality of counters in the block of storage.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Jonathan D. Bradbury, Daniel V. Rosa, Donald W. Schmidt
  • Patent number: 9740618
    Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ansu A. Abraham, Daniel V. Rosa, Donald W. Schmidt
  • Patent number: 9710184
    Abstract: A system and method for implementing a servicing instruction for a plurality of counters that includes determining a counter set based on the servicing instruction, whether access is authorized to the counter set, and a block of storage in a memory based on the service instruction. In response to the determining that the access is authorized, the system and method extracts the plurality of counters within the counter set in response to the determining that the access is authorized and storing the plurality of counters in the block of storage.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Jonathan D. Bradbury, Daniel V. Rosa, Donald W. Schmidt
  • Patent number: 9436608
    Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: September 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ansu A. Abraham, Daniel V. Rosa, Donald W. Schmidt
  • Publication number: 20160239421
    Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.
    Type: Application
    Filed: September 11, 2015
    Publication date: August 18, 2016
    Inventors: ANSU A. ABRAHAM, DANIEL V. ROSA, DONALD W. SCHMIDT
  • Publication number: 20160239419
    Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: ANSU A. ABRAHAM, DANIEL V. ROSA, DONALD W. SCHMIDT