Patents by Inventor Daniel Van Blerkom
Daniel Van Blerkom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090201407Abstract: CMOS image sensor with a rolling shutter that uses two separate clocks. One of the clocks is used during normal operation. When timing is changed, the other clock is started and used during an interim period to avoid distortion in the image. After that interim period, the new clock timing is coupled to the original clock circuit.Type: ApplicationFiled: April 6, 2009Publication date: August 13, 2009Inventor: Daniel Van Blerkom
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Publication number: 20090166545Abstract: An electronic imaging sensor, which has an improved immunity to noise caused by unwanted x-rays, images an object by collecting charge carriers produced in the sensor when the object is exposed to x-rays. One or more shielding areas are formed proximate the sensor to capture or sweep away any undesirable charge carriers generated by the unwanted x-rays. The shielding areas extend deeper beneath the surface of the sensor than the depth at which the desired charge carriers corresponding to the object being imaged is collected. The shielding areas capture charge carriers formed by the unwanted x-rays, which penetrate into the sensor to a greater depth than the depth at which the desired charge carriers are collected. In this way, the undesirable charge carriers are captured near the region where they are generated and before they migrate towards the surface where they can be collected and manifest as noise in the resulting image of the object.Type: ApplicationFiled: February 5, 2009Publication date: July 2, 2009Applicant: SCHICK TECHNOLOGIES, INC.Inventors: Stan Mandelkern, David Schick, Barmak Mansoorian, Daniel Van Blerkom
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Patent number: 7528873Abstract: CMOS image sensor with a rolling shutter that uses two separate clocks. One of the clocks is used during normal operation. When timing is changed, the other clock is started and used during an interim period to avoid distortion in the image. After that interim period, the new clock timing is coupled to the original clock circuit.Type: GrantFiled: December 28, 2005Date of Patent: May 5, 2009Assignee: Aptina Imaging CorporationInventor: Daniel Van Blerkom
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Patent number: 7523432Abstract: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.Type: GrantFiled: November 8, 2007Date of Patent: April 21, 2009Assignee: Sunplus Technology Co., Ltd.Inventors: Daniel Van Blerkom, Meng-Chang Yang
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Patent number: 7501631Abstract: An electronic imaging sensor, which has an improved immunity to noise caused by unwanted x-rays, images an object by collecting charge carriers produced in the sensor when the object is exposed to x-rays. One or more shielding areas are formed proximate the sensor to capture or sweep away any undesirable charge carriers generated by the unwanted x-rays. The shielding areas extend deeper beneath the surface of the sensor than the depth at which the desired charge carriers corresponding to the object being imaged is collected. The shielding areas capture charge carriers formed by the unwanted x-rays, which penetrate into the sensor to a greater depth than the depth at which the. desired charge carriers are collected. In this way, the undesirable charge carriers are captured near the region where they are generated and before they migrate towards the surface where they can be collected and manifest as noise in the resulting image of the object.Type: GrantFiled: October 7, 2005Date of Patent: March 10, 2009Assignee: Schick Technologies, Inc.Inventors: Stan Mandelkern, David Schick, Barmak Mansoorian, Daniel Van Blerkom
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Patent number: 7471231Abstract: A dual slope A/D converter uses two opposite sense ramps added to its differential input. The value in a digital counter is latched at the time when the two ramps intersect. This enables a more consistent switching point, allowing the amplifier to the linear over a larger part of its range.Type: GrantFiled: April 24, 2007Date of Patent: December 30, 2008Assignee: Forza Silicon CorporationInventors: Lin Ping Ang, Daniel Van Blerkom
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Publication number: 20080266155Abstract: A dual slope A/D converter uses two opposite sense ramps added to its differential input. The value in a digital counter is latched at the time when the two ramps intersect. This enables a more consistent switching point, allowing the amplifier to the linear over a larger part of its range.Type: ApplicationFiled: April 24, 2007Publication date: October 30, 2008Inventors: Lin Ping Ang, Daniel Van Blerkom
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Patent number: 7428015Abstract: An image sensor and offset-able reference voltage generator thereof are provided. The image sensor comprises a plurality of pixels, an offset-able reference voltage generator and a pixel sampling circuit. The pixel senses light from an image and generate an image signal. The offset-able reference voltage generator provides a reference voltage having a voltage offset. The pixel sampling circuit is coupled to the pixels and the offset-able reference voltage generator to sample the image signal and generate a pixel signal according to the reference voltage. The voltage offset of the reference voltage is able to compensate for the offset voltage in the process of generating the pixel signals.Type: GrantFiled: December 29, 2004Date of Patent: September 23, 2008Assignee: Sunplus Technology Co, Ltd.Inventors: Daniel Van Blerkom, I-Shiou Chen
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Publication number: 20080061389Abstract: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.Type: ApplicationFiled: November 8, 2007Publication date: March 13, 2008Applicant: SUNPLUS TECHNOLOGY CO., LTD.Inventors: Daniel Van Blerkom, Meng-Chang Yang
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Patent number: 7322020Abstract: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.Type: GrantFiled: January 25, 2005Date of Patent: January 22, 2008Assignee: Sunplus Technology Co., Ltd.Inventors: Daniel Van Blerkom, Meng-Chang Yang
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Patent number: 7292071Abstract: A circuit and method thereof for sampling/holding signal is provided. The signal sampling/holding circuit comprises a first signal sampling/holding device, a second signal sampling/holding device, a target signal and a reference voltage. First, the first signal sampling/holding device is supplied with the reference voltage and the target signal. The reference voltage is disconnected from the first signal sampling/holding device before the target signal is. Similarly, the reference voltage is disconnected from the second signal sampling/holding device before the target signal is. Thus the target signal is respectively sampled and held in the first signal sampling/holding device and the second signal sampling/holding device.Type: GrantFiled: January 21, 2005Date of Patent: November 6, 2007Assignee: Sunplus Technology Co., Ltd.Inventors: Daniel Van Blerkom, Steven Lei Huang, I-Shiou Chen, Te-Sung Su
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Publication number: 20070080300Abstract: An electronic imaging sensor, which has an improved immunity to noise caused by unwanted x-rays, images an object by collecting charge carriers produced in the sensor when the object is exposed to x-rays. One or more shielding areas are formed proximate the sensor to capture or sweep away any undesirable charge carriers generated by the unwanted x-rays. The shielding areas extend deeper beneath the surface of the sensor than the depth at which the desired charge carriers corresponding to the object being imaged is collected. The shielding areas capture charge carriers formed by the unwanted x-rays, which penetrate into the sensor to a greater depth than the depth at which the. desired charge carriers are collected. In this way, the undesirable charge carriers are captured near the region where they are generated and before they migrate towards the surface where they can be collected and manifest as noise in the resulting image of the object.Type: ApplicationFiled: October 7, 2005Publication date: April 12, 2007Applicant: SCHICK TECHNOLOGIES, INC.Inventors: Stan Mandelkern, David Schick, Barmak Mansoorian, Daniel Van Blerkom
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Patent number: 7151472Abstract: A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference voltage to an analog-to-digital converter (ADC) during a digitization operation. The reference voltage generator includes a variable voltage generator, a sample-and-hold circuit to sample a reference voltage prior to the pixel read-out operation or the digitization operation, and a buffer amplifier to drive the appropriate reference voltage to the relatively high impedance load presented by the S/H block and the variable impedance load provided by the ADC.Type: GrantFiled: February 20, 2003Date of Patent: December 19, 2006Assignee: Micron Technology, Inc.Inventors: Steve Huang, Daniel Van Blerkom, Sandor L. Barna, Giuseppe Rossi
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Patent number: 7084914Abstract: CMOS image sensor with a rolling shutter that uses two separate clocks. One of the clocks is used during normal operation. When timing is changed, the other clock is started and used during an interim period to avoid distortion in the image. After that interim period, the new clock timing is coupled to the original clock circuit.Type: GrantFiled: July 22, 2002Date of Patent: August 1, 2006Assignee: Micron Technology, Inc.Inventor: Daniel Van Blerkom
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Patent number: 7046079Abstract: A circuit for generating a reference voltage of an image sensor is provided. The circuit comprises a signal differential amplifier, a gain amplifier, a source follower and a clamp circuit. The signal differential amplifier is adapted for receiving and comparing a bias voltage and the reference voltage, and outputting a first voltage according to a comparison result. The gain amplifier is coupled to the signal differential amplifier, and is adapted for receiving the first voltage and outputting a second voltage. The source follower, coupled to the gain amplifier, and is adapted for receiving the second voltage and outputting the reference voltage. The clamp circuit is coupled to the source follower, and is adapted for receiving the reference voltage and limiting the reference voltage to below a clamp voltage.Type: GrantFiled: June 21, 2004Date of Patent: May 16, 2006Assignee: Sunsplus Technology Co., Ltd.Inventors: Daniel Van Blerkom, Meng-Chang Yang
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Patent number: 6977603Abstract: A non-uniform resistor is used with a flash A to D converter in order to provide an A to D output which is not linear. The nonlinearity of the A to D output is specially designed to carry out a predetermined correction of the signal.Type: GrantFiled: November 9, 2000Date of Patent: December 20, 2005Assignee: Micron Technology, Inc.Inventors: Sandor Barna, Daniel Van Blerkom, Eric R. Fossum
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Publication number: 20050237089Abstract: A circuit and method thereof for sampling/holding signal is provided. The signal sampling/holding circuit comprises a first signal sampling/holding device, a second signal sampling/holding device, a target signal and a reference voltage. First, the first signal sampling/holding device is supplied with the reference voltage and the target signal. The reference voltage is disconnected from the first signal sampling/holding device before the target signal is. Similarly, the reference voltage is disconnected from the second signal sampling/holding device before the target signal is. Thus the target signal is respectively sampled and held in the first signal sampling/holding device and the second signal sampling/holding device.Type: ApplicationFiled: January 21, 2005Publication date: October 27, 2005Inventors: Daniel Van Blerkom, Steven Lei Huang, I-Shiou Chen, Te-Sung Su
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Publication number: 20050240890Abstract: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.Type: ApplicationFiled: January 25, 2005Publication date: October 27, 2005Inventors: Daniel Van Blerkom, Meng-Chang Yang
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Publication number: 20050237400Abstract: An image sensor and offset-able reference voltage generator thereof are provided. The image sensor comprises a plurality of pixels, an offset-able reference voltage generator and a pixel sampling circuit. The pixel senses light from an image and generate an image signal. The offset-able reference voltage generator provides a reference voltage having a voltage offset. The pixel sampling circuit is coupled to the pixels and the offset-able reference voltage generator to sample the image signal and generate a pixel signal according to the reference voltage. The voltage offset of the reference voltage is able to compensate for the offset voltage in the process of generating the pixel signals.Type: ApplicationFiled: December 29, 2004Publication date: October 27, 2005Inventors: Daniel Van Blerkom, I-Shiou Chen
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Patent number: 6946987Abstract: A common operational amplifier for a pipeline circuit is provided. The common operational amplifier is used by the stage circuits of the pipeline circuit by turns according to a predetermined timing. The common operational amplifier comprises an operational amplifier circuit, a multiplexer circuit and a demultiplexer circuit. The multiplexer circuit is provided for selecting a signal set of a stage circuit to be amplified to couple to the operational amplifier circuit, and the demultiplexer circuit is provided for transmitting the amplified signal set to the corresponding stage circuit.Type: GrantFiled: February 1, 2005Date of Patent: September 20, 2005Assignee: Sunplus Technology Co., Ltd.Inventors: Daniel Van Blerkom, Steven Lei Huang, I-Shiou Chen, Te-Sung Su