Abstract: A combination multiplexer and tristate circuit. A multiplexer circuit may be configured to receive at least a first data input and a second data input, which are selected by at least a first select signal and a second select signal, respectively. A first circuit is configured to provide an output to an output node responsive to the data input that is selected by the corresponding select signal being active. The multiplexer circuit may further use a tristate circuit, which is also coupled to receive the first select signal and the second select signal. If neither the first select signal nor the second select signal are active, then the tristate circuit is configured to prevent the first circuit from providing an output to the output node.

Abstract: A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.

Abstract: A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.

Abstract: A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.

Abstract: A differential, CMOS receiver includes a transistor, coupled in parallel with an input transistor, which limits voltage differentials across an input transistor. A corresponding, similarly sized transistor balances current loading in a differential transistor. The transistor in parallel with the input transistor, whose drain is coupled directly to the power supply, quickly pulls the input transistor source and drain up to power supply voltage on an input transient from logical zero to a logical one which exceeds the power supply voltage. Another transistor coupled between the output node and the power supply rail defeats differential amplifier action when the input voltage is high out of its normal range.

Abstract: A CMOS bi-directional output driver normally operates at 3.3 volts but is capable of communicating with devices that operate at 5 volts.

Abstract: A cascode logic circuit provides a pair of differential output nodes that are pulled up by a pair of cross-coupled P-channel output transistors. The output nodes are connected to outputs of an N-channel combinatorial network that receives a differential input and functions to connect one of the output nodes to a positive supply and the other to ground, depending upon the differential input, thus providing a push-pull effect. The output nodes may be connected to the differential output of the combinatorial network by source-drain paths of separate N-channel transistors, with the gates of these transistors connected to the positive supply to capacitively isolate the output nodes from the combinatorial network; alternatively, the gates of these transistors may be clocked. A fully static latch is provided by adding cross-coupled N-channel transistors connecting the output nodes to ground, so the low side of the output is held down instead of being allowed to float.

Abstract: A clock buffer circuit for multiple phase complementary clocking signals that receives a plurality of corresponding enabling signals and generates a like plurality of clock signals in response thereto. Each clocking signal is generated by a buffer module including a resistor, a pull-up transistor and a pull-down transistor, which are connected in series between a positive power supply and ground, with the clocking signal being taken from the node between the pull-up and pull-down transistors. In each module, before the clocking signal shifts from a low state to a high, the pull-down transistor is on so that the clocking signal is at a low state. The pull-up transistor in each module is controlled by the corresponding enabling signal and is enabled to begin conducting at the time that the clocking signal is to shift to a high state.

Abstract: A semiconductor integrated oscillator circuit requiring higher impedances than are practical by integrated circuit technology and generally provided by discrete components external to the circuit are functionally provided in the integrated circuit by a "current mirror" circuit which provides the bias function separate from the signal function.