Abstract: A Hardware Description Language (HDL) comprising of a plurality of object commands, a plurality of compile commands and a plurality of comment styles is used in methods of electronic circuit design. An object command in the HDL defines a logic object, which can be as simple as a piece of wire or as complex as a priority-encoded arbitrator with a variable number of requesters. A Register Transfer Level (RTL) design in the HDL can be translated into a set of generic gates and instantiated library modules for design verification and synthesis. The design can also be translated to a target hardware description language such as Verilog-HDL or VHDL to feed into a conventional design flow.

Abstract: A novel packet switched routing architecture for establishing multiple, concurrent communications between a plurality of devices. Any number of devices are coupled to a central packet switched router via links. Due to the nature of these tightly coupled links, high data rates can be achieved between devices and the packet switched router with minimal pins. Any device can communicate to any other device via the packet switched router. The packet switched router has the capability of establishing multiple communication paths at the same time. Hence, multiple communications can occur simultaneously, thereby significantly increasing the overall system bandwidth.

Abstract: A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit.

Abstract: A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.

Abstract: A method and circuit providing for an accurate sampling of data on a high speed bus in a computer system. Utilizing a single clock source, functional units that are capable of supporting two clock input sources, and a routing technique that provides for a receiving unit to be clocked prior to a transmitting unit, data transfer can occur reliably and economically on a high speed bus. Synchronization within a particular unit is accomplished by providing serial edge-triggered registers that are triggered by the respective clock inputs.