Patents by Inventor Daniel Yen
Daniel Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176835Abstract: Implementations of the present disclosure include actions of receiving a search query, identifying potential search results responsive to the search query, the potential search results corresponding to digital content stored in one or more computer-readable storage media, determining that the potential search results include user-generated content that is generated using one or more computer-implemented social services, receiving data associated with the user-generated content, the data including one or more scores, determining, based on the one or more scores, that the user-generated content is to be provided as a search result, generating search results, the search results including web-based search results and at least a portion of the user-generated content, and transmitting the search results to a client computing device for display to the searching user.Type: ApplicationFiled: February 7, 2024Publication date: May 30, 2024Inventors: Daniel Belov, Matthew E. Kulick, Adam D. Bursey, David Yen, Maureen Heymans
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Patent number: 11934474Abstract: Implementations of the present disclosure include actions of receiving a search query, identifying potential search results responsive to the search query, the potential search results corresponding to digital content stored in one or more computer-readable storage media, determining that the potential search results include user-generated content that is generated using one or more computer-implemented social services, receiving data associated with the user-generated content, the data including one or more scores, determining, based on the one or more scores, that the user-generated content is to be provided as a search result, generating search results, the search results including web-based search results and at least a portion of the user-generated content, and transmitting the search results to a client computing device for display to the searching user.Type: GrantFiled: March 8, 2022Date of Patent: March 19, 2024Assignee: GOOGLE LLCInventors: Daniel Belov, Matthew E. Kulick, Adam D. Bursey, David Yen, Maureen Heymans
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Publication number: 20230339480Abstract: Provided are methods for robust fault tolerant architecture, which can include methods for determining transient faults and permanent faults. Some methods described also include applying one or more fault schemes, based on the determination of transient and permanent faults. Further provided are apparatuses for robust fault tolerant architecture, which can include apparatuses having a plurality of processors and cross connectors for determining fault states. Systems and computer program products are also provided.Type: ApplicationFiled: April 25, 2023Publication date: October 26, 2023Inventor: Daniel YEN
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Publication number: 20210040433Abstract: Hypoxia plays a central role in cancer progression and resistance to therapy. A microdevice platform is engineered to recapitulate the intratumor oxygen gradients that drive the heterogeneous hypoxic landscapes in solid tumors. The microdevice design features a “tumor section”-like culture by incorporating a cell layer between two diffusion barriers, where an oxygen gradient is established by cellular metabolism and physical constraints. The oxygen gradient is confirmed by numerical simulation and imaging-based oxygen sensor measurement. Spatially-resolved hypoxic signaling in cancer cells is also demonstrated through immunostaining, gene expression assay, and hypoxia-targeted drug treatment. The microdevice platform can accurately generate and control oxygen gradients, eliminates complex microfluidic handling, allows for incorporation of additional tumor components, and is compatible with high-content imaging and high-throughput applications.Type: ApplicationFiled: October 15, 2020Publication date: February 11, 2021Inventors: KEYUE SHEN, YUTA ANDO, DANIEL YEN, HOANG TA
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Patent number: 10829730Abstract: Hypoxia plays a central role in cancer progression and resistance to therapy. A microdevice platform is engineered to recapitulate the intratumor oxygen gradients that drive the heterogeneous hypoxic landscapes in solid tumors. The microdevice design features a “tumor section”-like culture by incorporating a cell layer between two diffusion barriers, where an oxygen gradient is established by cellular metabolism and physical constraints. The oxygen gradient is confirmed by numerical simulation and imaging-based oxygen sensor measurement. Spatially-resolved hypoxic signaling in cancer cells is also demonstrated through immunostaining, gene expression assay, and hypoxia-targeted drug treatment. The microdevice platform can accurately generate and control oxygen gradients, eliminates complex microfluidic handling, allows for incorporation of additional tumor components, and is compatible with high-content imaging and high-throughput applications.Type: GrantFiled: March 30, 2018Date of Patent: November 10, 2020Assignee: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Keyue Shen, Yuta Ando, Daniel Yen, Hoang Ta
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Publication number: 20180291330Abstract: Hypoxia plays a central role in cancer progression and resistance to therapy. A microdevice platform is engineered to recapitulate the intratumor oxygen gradients that drive the heterogeneous hypoxic landscapes in solid tumors. The microdevice design features a “tumor section”-like culture by incorporating a cell layer between two diffusion barriers, where an oxygen gradient is established by cellular metabolism and physical constraints. The oxygen gradient is confirmed by numerical simulation and imaging-based oxygen sensor measurement. Spatially-resolved hypoxic signaling in cancer cells is also demonstrated through immunostaining, gene expression assay, and hypoxia-targeted drug treatment. The microdevice platform can accurately generate and control oxygen gradients, eliminates complex microfluidic handling, allows for incorporation of additional tumor components, and is compatible with high-content imaging and high-throughput applications.Type: ApplicationFiled: March 30, 2018Publication date: October 11, 2018Inventors: KEYUE SHEN, YUTA ANDO, DANIEL YEN, HOANG TA
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Publication number: 20110121703Abstract: One or more embodiments presented herein include a light emitting system and/or device that can include a thermal management system. The thermal management system can provide for transport and/or dissipation of heat generated by a light emitting device.Type: ApplicationFiled: February 22, 2008Publication date: May 26, 2011Applicant: Luminus Devices, Inc.Inventors: Robert F. Karlicek, JR., Daniel Yen Chu, Joseph D. Whitney, Paul Panaccione, Warren P. Pumyea, Brian L. Stoffers, Michael A. Joffe, Alexei A. Erchak
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Patent number: 7295373Abstract: This specification discloses a power polarization beam combiner and its applications in fiber communications. The power polarization beam combiner uses the photonic band gap formed in a photonic crystal to produce a left-hand material with a negative refractive index and high dispersion rate. Using such properties of the photonic crystal, several beams with different wavelengths and polarizations are combined and output to a common port.Type: GrantFiled: May 14, 2004Date of Patent: November 13, 2007Assignee: Industrial Technology Research InstituteInventors: Chih-Tsung Shih, Chen-Bin Huang, Daniel Yen Chu, Yu-Chen Yu
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Patent number: 7067869Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.Type: GrantFiled: January 12, 2004Date of Patent: June 27, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wei Hua Cheng, Daniel Yen, Chit Hwei Ng, Marvin Liao
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Publication number: 20050101083Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.Type: ApplicationFiled: November 23, 2004Publication date: May 12, 2005Inventors: Chew Ang, Eng-Hua Lim, Randall Cha, Jia Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
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Publication number: 20050089777Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “l”. The re-flowed first opening lower width “l” being less than the pre-re-flowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “l”. Removing the patterned, re-flowed masking layer.Type: ApplicationFiled: November 12, 2004Publication date: April 28, 2005Inventors: Chew-Hoe Ang, Eng Lim, Randall Cha, Jia-Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
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Patent number: 6841441Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.Type: GrantFiled: January 8, 2003Date of Patent: January 11, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Eng-Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
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Publication number: 20040266155Abstract: A method of fabricating an ultra-small semiconductor structure comprising the following steps. A substrate having a lower dielectric layer and an overlying upper dielectric layer formed thereover is provided. Using a lithography process having a lithography limit, the upper dielectric layer is patterned to form a first opening exposing a portion of the lower dielectric layer. The first opening having exposed side walls and a width equal to the lithography limit. Sidewall spacers having a lower width are formed over the exposed side walls of the first opening. Using the sidewall spacers as masks, the lower dielectric layer is patterned to form a lower opening having a width less than the first opening width. The patterned upper dielectric layer is removed. An ultra-small semiconductor structure is formed within the lower opening. The ultra-small semiconductor structure having a width equal to the lithography limit minus twice the lower width of the sidewall spacer.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou, Daniel Yen
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Patent number: 6828082Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer.Type: GrantFiled: February 8, 2002Date of Patent: December 7, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew-Hoe Ang, Eng Hua Lim, Randall Cha, Jia-Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
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Patent number: 6803305Abstract: A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.Type: GrantFiled: April 10, 2002Date of Patent: October 12, 2004Assignee: Chartered Semiconductor Manufacturing LimitedInventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu, Ding Yi
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Publication number: 20040147087Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.Type: ApplicationFiled: January 12, 2004Publication date: July 29, 2004Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Wei Hua Cheng, Daniel Yen, Chit Hwei Ng, Marvin Liao
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Publication number: 20040132271Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.Type: ApplicationFiled: January 8, 2003Publication date: July 8, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Eng-Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
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Publication number: 20040077174Abstract: A method for forming a high aspect ratio via. In one embodiment, the present method comprises providing a first material into which a high aspect ratio via is to be formed. The present embodiment then deposits a first layer of a second material above the first material. Next, the present method recites forming an opening in the first layer of the second material. A second layer of the second material is then deposited above the first layer of the second material and into the opening formed into the first layer of the second material. The present embodiment then etches the second layer of the second material such that the opening extends through the second layer of the second material and through the first layer of the second material. In so doing, the opening is configured to have a profile conducive to the adherence of overlying material thereto.Type: ApplicationFiled: October 18, 2002Publication date: April 22, 2004Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., AGILENT TECHNOLOGIES, INC.Inventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu
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Patent number: 6713335Abstract: A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.Type: GrantFiled: August 22, 2002Date of Patent: March 30, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Daniel Yen, Ching-Thiam Chung, Wei Hua Cheng, Chester Nieh, Tong Boon Lee
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Publication number: 20040038466Abstract: A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.Type: ApplicationFiled: August 22, 2002Publication date: February 26, 2004Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Daniel Yen, Ching-Thiam Chung, Wei Hua Cheng, Chester Nieh, Tong Boon Lee