Patents by Inventor Danilo Caraccio

Danilo Caraccio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses and methods for securing an access protection scheme
    Patent number: 11030122
    Abstract: A device includes a memory. The device also includes a controller. The controller includes a register configured to store an indication of whether an ability of a received command to alter an access protection scheme of the memory is enabled. The received command may alter the access an access protection scheme of the memory responsive to the indication.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Graziano Mirichigni
  • DATA STATE SYNCHRONIZATION
    Publication number: 20210166775
    Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 3, 2021
    Inventors: Paolo Amato, Marco Dallabora, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri
  • Methods and apparatuses for executing a plurality of queued tasks in a memory
    Patent number: 11023167
    Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio, Antonino Pollio
  • Hybrid memory system interface
    Patent number: 10977198
    Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Marco Dallabora, Daniele Balluchi, Paolo Amato, Luca Porzio
  • Memory management
    Patent number: 10956290
    Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Marco Dallabora, Emanuele Confalonieri, Paolo Amato, Daniele Balluchi, Danilo Caraccio
  • Data state synchronization
    Patent number: 10943659
    Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Marco Dallabora, Paolo Amato, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri
  • MULTI-PARTITIONING OF MEMORIES
    Publication number: 20210064261
    Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
    Type: Application
    Filed: September 14, 2020
    Publication date: March 4, 2021
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Federico Tiziani
  • Data state synchronization involving memory cells having an inverted data state written thereto
    Patent number: 10916324
    Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Marco Dallabora, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri
  • Storage class memory status
    Patent number: 10891223
    Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Graziano Mirichigni, Danilo Caraccio
  • Command queuing
    Patent number: 10884661
    Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Victor Y. Tsai, Danilo Caraccio, Daniele Balluchi, Neal A. Galbo, Robert Warren
  • HYBRID MEMORY SYSTEM
    Publication number: 20200409607
    Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • WIRELESS MEMORY INTERFACE
    Publication number: 20200389778
    Abstract: Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag are provided. A wireless memory host includes a radio and controller. The controller generates vendor-agnostic commands to access a register-based interface that ultimately results in access to the non-volatile memory.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: Graziano Mirichigni, Danilo Caraccio
  • TRANSACTION METADATA
    Publication number: 20200348999
    Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Inventors: Graziano Mirichigni, Marco Sforzin, Paolo Amato, Danilo Caraccio
  • Latency-based storage in a hybrid memory system
    Patent number: 10809942
    Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • HYBRID MEMORY SYSTEM
    Publication number: 20200301841
    Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • HYBRID MEMORY SYSTEM
    Publication number: 20200293211
    Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 17, 2020
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • Multi-partitioning of memories
    Patent number: 10776031
    Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Federico Tiziani
  • Wireless memory interface
    Patent number: 10779147
    Abstract: Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag include: detecting, via a wireless memory host, a wireless memory tag; providing a vendor-agnostic command to the wireless memory tag to affect a change in a register-based interface of the wireless memory tag, wherein the change results in reading data from non-volatile memory of the wireless memory tag, writing data to the non-volatile memory of the wireless memory tag, or both.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Danilo Caraccio
  • Transaction metadata
    Patent number: 10733046
    Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Marco Sforzin, Paolo Amato, Danilo Caraccio
  • DATA RELOCATION IN HYBRID MEMORY
    Publication number: 20200233585
    Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Inventors: Emanuele Confalonieri, Marco Dallabora, Paolo Amato, Danilo Caraccio, Daniele Balluchi