Abstract: This document relates to memory access profiling. One example relates to a method or technique that can include obtaining samples collected when executing an application, the samples comprising sampled register values that were present in one or more registers of a processor when the samples were collected. The method or technique can also include identifying sampled instructions of the application that were executing when the samples were collected and other instructions of the application. The method or technique can also include evaluating the sampled instructions and one or more of the other instructions using the sampled register values to identify memory accesses by the application. The method or technique can also include outputting the identified memory accesses.

Abstract: A method of adding a custom vocabulary to a transcription system includes receiving a custom vocabulary at an ASIRW module. The method further includes tokenizing the custom vocabulary with the ASIRW module. The method further includes creating a new WFST (weighted finite-state transducer) with the ASIRW module. The method further includes transcribing audio using the new WFST with the ASIRW module.

Abstract: The discussion relates to automatically providing information about what code sequences contribute to a length of time a program takes to execute. One example can collect context switch and ready thread event tracing data from a program over a period of interest and identify time blocks of program threads from the period of interest. The example can distinguish individual time blocks that contribute to execution time for the period of interest from other individual time blocks that do not contribute to the execution time.

Abstract: A computing device is provided, including a processor configured to execute an application-under-test including a plurality of tasks. Each task may be executed in one or more task instances. The processor may determine respective performance data for the one or more task instances of each task. The processor may output, for display on a display, a graphical user interface (GUI) including a statistical representation of the performance data. The processor may receive, at the GUI, a selection of a task executed in a plurality of selected task instances in the application-under-test. The selected task instances may be executed in selected task execution time intervals that are at least partially non-contiguous in time. The processor may generate an aggregated view of the corresponding performance data for the selected task instances aggregated over the selected task execution time intervals. The processor may output the aggregated view for display at the GUI.

Abstract: The discussion relates to automatically providing information about what code sequences contribute to a length of time a program takes to execute. One example can collect context switch and ready thread event tracing data from a program over a period of interest and identify time blocks of program threads from the period of interest. The example can distinguish individual time blocks that contribute to execution time for the period of interest from other individual time blocks that do not contribute to the execution time.

Abstract: A computing device is provided, including a processor configured to execute an application-under-test including a plurality of tasks. Each task may be executed in one or more task instances. The processor may determine respective performance data for the one or more task instances of each task. The processor may output, for display on a display, a graphical user interface (GUI) including a statistical representation of the performance data. The processor may receive, at the GUI, a selection of a task executed in a plurality of selected task instances in the application-under-test. The selected task instances may be executed in selected task execution time intervals that are at least partially non-contiguous in time. The processor may generate an aggregated view of the corresponding performance data for the selected task instances aggregated over the selected task execution time intervals. The processor may output the aggregated view for display at the GUI.

Abstract: High-performance tracing can be achieved for an input program having a plurality of instructions. Techniques such as executable instruction transcription can enable execution of a plurality of instructions at a time via a run buffer. Execution information can be extracted via run buffer execution. Fidelity of execution can be preserved by executing instructions on the target processor. Other features, such as an executable extraction instruction ensemble, branch interpretation, and relative address compensation can be implemented. High quality instruction tracing can thus be achieved without the usual performance penalties.

Abstract: High-performance tracing can be achieved for an input program having a plurality of instructions. Techniques such as executable instruction transcription can enable execution of a plurality of instructions at a time via a run buffer. Execution information can be extracted via run buffer execution. Fidelity of execution can be preserved by executing instructions on the target processor. Other features, such as an executable extraction instruction ensemble, branch interpretation, and relative address compensation can be implemented. High quality instruction tracing can thus be achieved without the usual performance penalties.

Abstract: A database system comprises: a data store containing a database comprising records ordered according to a first key field, and a search index of the first key field. The database system also comprises a replica data store, containing a replica copy of the database, with the records ordered according a second key field, different from the first key field, and a search index of the second key field. A server is configured to receive a request to access the records, and to access the records using the replica copy if the request includes a criterion based on values of the second key field.

Abstract: A charge sharing circuit for generating a calibration voltage. The circuit comprises a calibration capacitor for providing at an upper terminal of the calibration capacitor the calibration voltage. The circuit further comprises a series connection of a plurality of N switches, wherein N is an integer>2, and a plurality of at least N?1 switching capacitors. Each switching capacitor is coupled to one connecting node connecting two of the N switches. One side of the series connection of the plurality of N switches is coupled to the upper terminal of the calibration capacitor and the other side of the series connection of the N switches is coupled to a fixed voltage. The circuit is configured to transmit at least two clock signals to selectively drive at least two distinct subsets of the switches. There is further provided a corresponding method and a corresponding design structure.

Abstract: Methods for dynamically instrumenting a program while the program is executing are described. In some embodiments, profiling hooks may be selectively inserted into and removed from a program while the program is running. The hooks may gather profiling information, such as the frequency and duration of function calls, for a selected set of functions. The hooks may be inserted into the program without requiring a special build or modifications to the binary by modifying machine-level instructions for the program stored in system memory. The ability to selectively insert instrumentation into the machine-level instructions stored in the system memory allows a set of functions to be selected during execution of the program and hooks for each function of the set of functions to be dynamically inserted or removed during execution of the program to precisely capture profiling information for the set of functions.

Abstract: The present invention relates to a successive approximation register analog-to-digital converter (SAR ADC) for providing a digital approximation of a sampled differential input signal as a result of a successive approximation operation. The SAR ADC comprises a first comparison stage configured to perform a first set of decision steps of the successive approximation operation and a second comparison stage configured to perform a second set of decision steps of the successive approximation operation. Furthermore, the SAR ADC comprises a regulation circuit configured to adjust the common mode of the input signal towards a target common mode before the second comparison stage performs the second set of decision steps. The present invention further relates to a corresponding method and a corresponding design structure.

Abstract: A linear reference analog to digital converter (ADC) network may include a first ADC operatively connected to a first sample and hold circuit. The linear reference ADC network may be configured to receive an input signal from the first sample and hold circuit and sample the input signal with a harmonic distortion. The linear reference ADC network may further include a reference ADC operatively connected to a second sample and hold circuit and configured to receive the input signal and sample the input signal with a second harmonic distortion. The linear reference ADC network may further include a combining module operatively connected to the first ADC and the reference ADC, the combining module configured to equalize a linearity of an output of the first ADC to a linearity of an output of the reference ADC, and output a combined output signal, and a circuit configured to output a calibrated output signal having calibrated harmonic distortion content.

Abstract: Systems, methods and computer program products that provide a framework for the creation, editing, manipulation and use of model-based, multidimensional analysis services (MAS) cubes and using substitute dimensions in such cubes are disclosed. To permit a user to obtain better and automatic access to business intelligence, a method of generating a model-based MAS cube comprises creating a data source comprising a data warehouse in the memory via the processor, creating a data source view providing a dimension, a fact and an outrigger from the created data source, and creating the MAS cube comprising at least one measure group. Using substitute dimensions comprises finding all relevant substitutions for a measure group, creating a table for the measure group in the data source view, adding a property as the primary key of the substitute dimension and generating a query containing an inner join logical link between the substitute and original dimension.

Abstract: Methods for dynamically instrumenting a program while the program is executing are described. In some embodiments, profiling hooks may be selectively inserted into and removed from a program while the program is running. The hooks may gather profiling information, such as the frequency and duration of function calls, for a selected set of functions. The hooks may be inserted into the program without requiring a special build or modifications to the binary by modifying machine-level instructions for the program stored in system memory. The ability to selectively insert instrumentation into the machine-level instructions stored in the system memory allows a set of functions to be selected during execution of the program and hooks for each function of the set of functions to be dynamically inserted or removed during execution of the program to precisely capture profiling information for the set of functions.

Abstract: A cutting tool (10) includes a cutting portion (14) and a clamping mechanism (16) configured to be brought between an unclamped position in which a cutting insert (12) is removable from the cutting portion (14), and a clamped position in which the cutting insert (12) is clamped to the cutting portion (14). The clamping mechanism (16) includes a clamp (20) and a cam shaft (18). The clamp (20) is formed with a growth pattern region (20C6) having a varying diameter. The cam is formed with a growth pattern region (18C1) having a varying diameter. The growth pattern regions (20C6, 18C4) are configured for engaging each other to transform rotary motion of the cam shaft (18) into linear motion of the clamp (20) to thereby move the clamping mechanism (16) into the clamped position.

Abstract: An indexable double-negative cutting insert includes an index axis A, two opposing end surfaces, a peripheral side surface which extends therebetween, and opposing side cutting edges formed between the end surfaces and the peripheral side surface. A median plane P is located midway between the end surfaces, passes through the peripheral side surface and is perpendicular to the index axis. The peripheral side surface includes at least one protrusion which extends in an outward direction relative to the index axis, in a plan view of either end surface. The protrusion includes two side abutment surfaces which converge in the outward direction towards the median plane P. In each cross-section perpendicular to the median plane, which cross-section passes through both opposing side cutting edges and also the at least one protrusion, no portion of the peripheral surface is inward of an imaginary line connecting the opposing side cutting edges.

Abstract: A double-sided indexable threading cutting insert includes two opposite end surfaces and a common periphery extending therebetween. The periphery includes exactly five identical peripheral sections and exactly five identical peripheral segments. Each peripheral segment extends between two adjacent peripheral sections and each peripheral section includes two adjacent abutment sections located between two rake faces. In a plan view of each end surface, each abutment section lies on a portion of an imaginary five-pointed star which includes five outer vertices alternating with five inner vertices. The cutting insert includes five cutting portions, each cutting portion is associated with a respective outer vertex, each cutting portion extends outwardly, and each cutting portion includes two opposite cutting tips.

Abstract: A tangential cutting insert has two opposing side surfaces and a peripheral surface extending between the side surfaces. The peripheral surface has four identical end surfaces. The intersections of the end and side surfaces include major cutting edges. The intersection of end surfaces and adjacent end surfaces include minor cutting edges. Each of the major and minor cutting edges has a rake surface extending in an inward direction of the cutting insert. In a side view of the cutting insert the major cutting edges are concave.