Abstract: A processor for use in a parallel computing system. The processor contains: a memory for storing operand values; an arithmetic logic unit (ALU) for performing arithmetic logic operations on operand values; a multiplier, separate from the ALU and coupled to the memory, for generating arithmetic products of a first operand value and a second operand values; and a match unit, separate from the ALU and coupled to the memory, for detecting matches between a predetermined bit pattern and a sequence of bits retrieved from the memory. The match unit also generates a count value indicating a number of detected matches between the predetermined bit pattern and subsequences of bits within the sequence of bits. The first operand value contains the bit pattern and the second operand contains the sequence of bits.

Abstract: MIMD and pipeline processing is executed by entering data and control signals into processing chips in the form of optical signals, and entering multi-bit information (data and control signals) in parallel and at high speed on the basis of non-coherence of light beams. The efficiency of MIMD processing function has been improved by expanding data transfer buses between processors and output buses in place of data and control signal input buses that have become unnecessary. A processing chip for receiving optical signals consists of a large number of cells dedicated for vector computations, and/or a large number of cells dedicated for vector computations and/or cells dedicated for arithmetic and logical computations. A processing chip for wide applications ranging from vector computations to logical computations by employing a construction combining both processors.

Abstract: A routing process for a single-instruction-multiple-data (SIMD) multi-level hierarchical network of nodes, which are arranged in clusters and interconnected by dual, unidirectional channels, are used to send data packets including routing address information during a succession of routing cycles from transmitting ones to receiving ones of a large number of parallel processors (e.g., 4096 processors arranged in a hierarchy of 8 cabinets, each of which contains a cluster of 8 circuit boards, with each circuit board containing a cluster of 64 processors). Each of the nodes includes a storage buffer having a capacity equal to a given number which is one more than the total number of channels terminating at that node. This routing process guarantees prevention of deadlock between levels and buffer overflow, and offers high-speed, low-cost interprocessor communication for SIMD computers.

Abstract: In a color TV receiver, a first digital signal of "m" bits represents high frequency component of combed luminance signal, and a second digital signal of "m" bits represents combed chrominance component. The "k" most significant bits of the first signal (where "k" is less than "m") are fed to respective inputs of a first "or" gate, while the "j" most significant bits of the second signal (where "j" is less than, or equal to, "m") are fed to respective inputs of a second "or" gate. The "or" gate outputs are fed, without delay difference, to inputs of a first "and" gate, and are fed, with a delay difference of 90.degree. at color subcarrier frequency, to inputs of a second "and" gate. Sequence recognition apparatus, responsive to the outputs of both "and" gates, develops a correlation indication in response to existence of predetermined sequences of outputs from one or both "and" gates.

Abstract: For real time processing of wide-band signals, the magnitude, C, of the vector sum of substantially orthogonal component vectors A and B is performed with minimal circuitry by employing the algorithmC=A+KB A>BandC=B+KA A>Bwhere A and B are the magnitudes of vectors A and B and the factor K is related to the phase angle .theta. of the vector sum relative to the axis vector A. For precise values of C, the value K is determined from the equationK=(1-cos .theta.)/sin .theta. A>BK=(1-sin .theta.)/cos .theta. A<B.

Abstract: An auto-flesh circuit for a TV receiver is described which operates an I and Q color mixture signals to produce flesh corrected color mixture signals I' and Q'. The received I and Q signals are demodulated in respective circuitry to generate the magnitude and angle of their vector sum. The angle values are applied as address codes to a ROM programmed to produce the sines and cosines of the applied address codes. For address code angles corresponding to chrominance signals representing flesh tones, the values of the programmed sines and cosines correspond to values of flesh corrected chrominance angles. The sine and cosine values output by the ROM are then multiplied by the magnitude of the vector sum (chrominance magnitude) to produce corrected Q' and I' color mixture signals respectively.

Abstract: As a signal seeking tuner tunes through a number of channels to locate the next active (useable) channel, the display screen of a television receiver is blanked when the receiver is tuned between channels or to an inactive (unuseable) channel for which video signal information is substantially absent. Superimposed over the blanked screen background is a moveable tuning indicator bar, the position of which indicates the channel to which the receiver is tuned. The blanking of the screen prevents the tuning indication from being obscured by background noise.

Abstract: A color TV receiver designed to digitally process I and Q color mixture signals incorporates chroma gain control, static tint control and autoflesh in the circuitry for converting the I and Q signals to (R-Y), (B-Y) and (G-Y) for R,G,B matrixing. The magnitude and angle of the vector sum of I and Q are first determined. The angles are then adjusted for static tint control and then applied to a ROM which is programmed to output angles adjusted for fleshtones. Angles from the autoflesh ROM are applied to a summing circuit which algebraically adds to the flesh corrected angle, angle values corresponding to the angular displacement between the I axes and the (R-Y), (B-Y) and (G-Y) axes. The angles produced by the summing circuit are applied to a look-up ROM which produces the cosine values of the applied angles.The magnitude signal is amplified by coefficients which relate the I and Q signals to (R-Y), (B-Y) and (G-Y) components and which coefficients may be amplified by a chroma gain signal.

Abstract: A signal-seeking tuning system for a television receiver scans the VHF and UHF signal bands until a present TV channel signal is detected. Tuning voltage is developed by a digital-to-analog converter in response to a binary word stored in an up-down counter. The value of the binary word increases when a scan-up signal is applied and decreases when a scan-down signal is applied. Scanning is stopped by inhibiting changing of the binary word when a valid sequence of AFT signals is detected.Thereafter, the tuning voltage is compensated for drifts by incrementing or decrementing the binary word whenever the AFT signal departs from a predetermined condition. This correction is inhibited, however, when the RF carrier signal is lost so that the desired tuning is not also lost, whereby the selected channel is still tuned when the RF carrier signal reappears.

Abstract: In television (TV) receivers, the VHF-TV band including channel 2-13 is perceived by most viewers as being a single TV band even though it is in fact partitioned into lower and upper frequency portions, including channels 2-6 and 7-13, respectively, which are separated by a gap. Voltage controlled tuning systems for such TV receivers employ a tuning voltage which varies over substantially the same range of magnitudes from a lower voltage to a higher voltage for each of the frequency portions of the VHF band. Accordingly, conventional channel indicators responsive to the magnitude of the tuning voltage partition the bands to avoid ambiguity in the channel indication. In the present arrangement, a tuning indicator produces an on-screen bar display having a position which is indicative of the selected channel for all VHF channels as if the VHF frequency band was continuous and not partitioned thereby being consistent with the perception of most viewers.

Abstract: A signal-seeking tuning system for a television receiver scans the VHF and UHF signal bands until a present TV channel signal is detected. Tuning voltage is developed by a digital-to-analog converter in response to a binary word stored in an up/down counter. The value of the binary word increases when a scan-up signal is applied and decreases when a scan-down signal is applied. Band signals are automatically sequenced to the next higher frequency band when the binary word "rolls-over" from a maximum to a minimum value, or to the next lower frequency band when the binary word rolls-over from its minimum to its maximum value. Scanning is stopped by inhibiting changing of the binary word when a valid sequence of AFT signals is detected.Thereafter, the tuning voltage is compensated for drifts by incrementing or decrementing the binary word whenever the AFT signal departs from a predetermined condition.

Abstract: A television (TV) receiver which receives TV signals in a plurality of TV frequency bands includes apparatus for developing an accentuated and uncontaminated on-screen tuning indication. Specifically, a blanking device is responsive to a tuning signal for eliminating the display of a portion of the TV picture for the duration of a pulse signal. The pulse signal is delayed in time relative to a deflection signal by a time related to the tuning signal so that a blanked bar is generated in the TV picture. A tuning indicator device causes a predetermined display unaffected by the TV picture during the blanked portion of the TV picture.