Patents by Inventor Danny Echtle

Danny Echtle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming strapless anti-fuse structure
    Patent number: 6444502
    Abstract: An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: September 3, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Ivan Sanchez, Danny Echtle, Landon B. Vines
  • Metal to amorphous silicon to metal anti-fuse structure
    Patent number: 6016001
    Abstract: An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: January 18, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ivan Sanchez, Danny Echtle, Landon B. Vines