Abstract: A transmission system includes a sending apparatus and N signal channels, where N?2, and N is an integer. The sending apparatus includes a first apparatus, and the first apparatus is configured to: obtain N to-be-transmitted signals and an encoding coefficient group, where the N to-be-transmitted signals are represented as an N×1 signal matrix X, and the encoding coefficient group is represented as an N×N orthogonal encoding matrix T; process the N to-be-transmitted signals based on the encoding coefficient group to generate N encoded first signals, where the N encoded first signals are represented as a signal matrix Y; and send the N encoded first signals to the N signal channels, where a signal on each signal channel corresponds to an element in a row of the signal matrix Y.

Abstract: Embodiments of this application provide a balance-unbalance conversion apparatus. The apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.

Abstract: A connector, a frame device, and a connector assembly method. Some terminal modules in the connector provided in the present disclosure are removed, or some terminal pairs in the terminal module are removed, so that a quantity of terminal pairs included in the connector is reduced without changing an outline dimension of the connector, thereby ensuring an original docking capability of the connector. In addition, a serial connector may be formed based on different quantities of removed terminal modules or removed terminal pairs. In this way, in the frame device, a user may select a connector of a corresponding specification based on an actual specification of a board, instead of selecting connectors of a high specification uniformly.

Abstract: This application discloses an optical backplane system, which includes a first upper-level optical interconnection module, a first lower-level optical interconnection module, and a second lower-level optical interconnection module. The first upper-level optical interconnection module includes M1 first interfaces and N1 second interfaces in connection relationships. The first lower-level optical interconnection module includes L1 third interfaces and K1 fourth interfaces in connection relationships. The second lower-level optical interconnection module includes L2 third interfaces and K2 fourth interfaces in connection relationships. The first upper-level optical interconnection module is connected to one of the L1 third interfaces of the first lower-level optical interconnection module by using one of the N1 second interfaces.

Abstract: Embodiments of this application provide a balance-unbalance conversion apparatus. The apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.

Abstract: This application discloses an optical backplane system, which includes a first upper-level optical interconnection module, a first lower-level optical interconnection module, and a second lower-level optical interconnection module. The first upper-level optical interconnection module includes M1 first interfaces and N1 second interfaces in connection relationships. The first lower-level optical interconnection module includes L1 third interfaces and K1 fourth interfaces in connection relationships. The second lower-level optical interconnection module includes L2 third interfaces and K2 fourth interfaces in connection relationships. The first upper-level optical interconnection module is connected to one of the L1 third interfaces of the first lower-level optical interconnection module by using one of the N1 second interfaces.

Abstract: A data processing apparatus includes a scrambling processing unit and a sending unit. The scrambling processing unit is configured to generate a Pseudo-Random Binary Sequence (PRBS), perform a modulo-2 addition on the pseudo-random sequence and data frame data to scramble the data frame data including first load data, use one section of a part of the pseudo-random sequence on which the modulo-2 addition is performed with the data frame data as an identification sequence, and carry status information corresponding to the identification sequence in frame header information. The sending unit is configured to send the frame header information carrying the status information and the scrambled first load data. Through the scrambling process, continuous run-lengths of “1” and “0” in the data frame data are quite short, while basically the same probability of occurrence is maintained, which is favorable to transmission of the data frame data, thereby alleviating error code problems.

Abstract: A data processing apparatus includes a scrambling processing unit and a sending unit. The scrambling processing unit is configured to generate a Pseudo-Random Binary Sequence (PRBS), perform a modulo-2 addition on the pseudo-random sequence and data frame data to scramble the data frame data including first load data, use one section of a part of the pseudo-random sequence on which the modulo-2 addition is performed with the data frame data as an identification sequence, and carry status information corresponding to the identification sequence in frame header information. The sending unit is configured to send the frame header information carrying the status information and the scrambled first load data. Through the scrambling process, continuous run-lengths of “1” and “0” in the data frame data are quite short, while basically the same probability of occurrence is maintained, which is favorable to transmission of the data frame data, thereby alleviating error code problems.

Abstract: A data processing apparatus includes a scrambling processing unit and a sending unit. The scrambling processing unit is configured to generate a Pseudo-Random Binary Sequence (PRBS), perform a modulo-2 addition on the pseudo-random sequence and data frame data to scramble the data frame data including first load data, use one section of a part of the pseudo-random sequence on which the modulo-2 addition is performed with the data frame data as an identification sequence, and carry status information corresponding to the identification sequence in frame header information. The sending unit is configured to send the frame header information carrying the status information and the scrambled first load data. Through the scrambling process, continuous run-lengths of “1” and “0” in the data frame data are quite short, while basically the same probability of occurrence is maintained, which is favorable to transmission of the data frame data, thereby alleviating error code problems.

Abstract: A data processing apparatus includes a scrambling processing unit and a sending unit. The scrambling processing unit is configured to generate a Pseudo-Random Binary Sequence (PRBS), perform a modulo-2 addition on the pseudo-random sequence and data frame data to scramble the data frame data including first load data, use one section of a part of the pseudo-random sequence on which the modulo-2 addition is performed with the data frame data as an identification sequence, and carry status information corresponding to the identification sequence in frame header information. The sending unit is configured to send the frame header information carrying the status information and the scrambled first load data. Through the scrambling process, continuous run-lengths of “1” and “0” in the data frame data are quite short, while basically the same probability of occurrence is maintained, which is favorable to transmission of the data frame data, thereby alleviating error code problems.

Abstract: A data processing apparatus includes a scrambling processing unit and a sending unit. The scrambling processing unit is configured to generate a Pseudo-Random Binary Sequence (PRBS), perform a modulo-2 addition on the pseudo-random sequence and data frame data to scramble the data frame data including first load data, use one section of a part of the pseudo-random sequence on which the modulo-2 addition is performed with the data frame data as an identification sequence, and carry status information corresponding to the identification sequence in frame header information. The sending unit is configured to send the frame header information carrying the status information and the scrambled first load data. Through the scrambling process, continuous run-lengths of “1” and “0” in the data frame data are quite short, while basically the same probability of occurrence is maintained, which is favorable to transmission of the data frame data, thereby alleviating error code problems.

Abstract: A system for measuring signals includes: a simulating device, adapted to simulate equalization for an incoming signal of an SERDES receiving chip and generate a response signal, and a feature output device, adapted to output the feature information of the response signal. The invention also discloses a method and a device for measuring signals.