Abstract: A method of manufacturing a device, comprising printing an aqueous solution or dispersion comprising an electronically functional substance, for example a conducting polymer such as PEDOT-PSS, and a surface tension reducing agent onto predetermined portions of a hydrophobic surface, for example formed by a ferroelectric polymer layer. The conducting polymer can form conductive tracks on either side of the ferroelectric layer to form a memory device.

Abstract: A memory device comprising a layer of piezoelectric material and a layer of ferroelectric material clamped together such that a voltage applied to one layer results in a voltage being generated across the other layer. The method of data storage and retrieval comprising the steps of: providing a layer of ferroelectric material, providing a layer of piezoelectric material, clamping the two layers together, storing data by internally polarising the ferroelectric material in one of two stable directions in accordance with the data to be stored, and retrieving stored data by applying a non-polarising voltage to one layer and detecting a resultant voltage from the other layer. Preferably, the piezoelectric material is implemented as a ferroelectric material.

Abstract: A semiconductor device comprising an n-channel region and a p-channel region formed on a common substrate, both channel regions having a source and a drain, the device further comprising a gate electrode common to both channel regions and spaced from the substrate by an area of non-polarising dielectric material arranged under the gate electrode.

Abstract: A device comprising a layer of piezoelectric material and a layer of ferroelectric material clamped together such that a voltage applied to one layer results in a voltage being generated across the other layer. Examples are given of the implementation of analogue components such as an amplifier, a transformer, an inverter and a comparator. For the comparator, the device has a third layer of material clamped together with the other two layers, the third layer being a ferroelectric material.

Abstract: A memory device including an n-channel transistor and p-channel transistor, both transistors having a source, a drain and a gate, the source and drains of the transistors being connected in series and the gates of the transistors being connected together, with each transistor having a ferroelectric material separating the gate from the source and drain thereof. Preferably a single ferroelectric material acts as the ferroelectric material for both transistors and a single gate acts as the gate for both transistors. Beneficially the device includes a single substrate having an n-type source, an n-type drain, a p-type source and a p-type drain formed in a surface thereof and a single area of the substrate which separates all of these regions from each other has intrinsic doping only. The invention also relates to a method of manufacturing such memory devices.

Abstract: A device comprising a layer of piezoelectric material and a layer of ferroelectric material clawed together such that a voltage applied to one layer results in a voltage being generated across the other layer. Examples are given of the implementation of analogue components such as an amplifier, a transformer, an inverter and a comparator, For the comparator, the device has a third layer of material clamped together with the other two layers, the third layer being a ferroeleotric material.

Abstract: A memory device comprising a layer of piezoelectric material and a layer of ferroelectric material clamped together such that a voltage applied to one layer results in a voltage being generated across the other layer. The method of data storage and retrieval comprising the steps of: providing a layer of ferroelectric material, providing a layer of piezoelectric material, clamping the two layers together, storing data by internally polarising the ferroelectric material in one of two stable directions in accordance with the data to be stored, and retrieving stored data by applying a non-polarising voltage to one layer and detecting a resultant voltage from the other layer. Preferably, the piezoelectric material is implemented as a ferroelectric material.

Abstract: A memory device comprising an n-channel transistor and p-channel transistor, both transistors having a source, a drain and a gate, the source and drains of the transistors being connected in series and the gates of the transistors being connected together, with each transistor having a ferroelectric material separating the gate from the source and drain thereof. Preferably a single ferroelectric material acts as the ferroelectric material for both transistors and a single gate acts as the gate for both transistors. Beneficially the device comprises a single substrate having an n-type source, an n-type drain, a p-type source and a p-type drain formed in a surface thereof and a single area of the substrate which separates all of these regions from each other has intrinsic doping only. The invention also relates to a method of manufacturing such memory devices.